KR920003448A - 바이폴라 소자의 메몰층 형성방법 - Google Patents
바이폴라 소자의 메몰층 형성방법 Download PDFInfo
- Publication number
- KR920003448A KR920003448A KR1019900010597A KR900010597A KR920003448A KR 920003448 A KR920003448 A KR 920003448A KR 1019900010597 A KR1019900010597 A KR 1019900010597A KR 900010597 A KR900010597 A KR 900010597A KR 920003448 A KR920003448 A KR 920003448A
- Authority
- KR
- South Korea
- Prior art keywords
- forming
- buried layer
- bipolar device
- nitride film
- film
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims description 4
- 150000004767 nitrides Chemical class 0.000 claims 3
- -1 nitride nitride Chemical class 0.000 claims 1
- 239000000758 substrate Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Bipolar Transistors (AREA)
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명의 공정 단면도.
제3도 (B)는 본 발명의 언더 컷 상태도.
Claims (2)
- 기판위에 얇은 산화막과 질화막을 차례로 형성하는 단계와, 상기 산화막과 질화막을 마스크로하여 메몰층을 형성하는 포토/에치단계, 상기 메몰층에 이온주입과 드라이브-인을 행하여 다음 공정의 포토 얼라인에 필요한 단차를 형성하는 단계, 산화막과 질화막을 제거하고 에피층을 형성하는 단계가 순차적으로 포함됨을 특징으로 하는 바이폴라 소자의 메몰층 형성방법.
- 제1항에 있어서, 산화막화 질화막은 각각 1000Å 정도로함을 특징으로 하는 바이폴라 소자의 메몰층 형성방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019900010597A KR930004121B1 (ko) | 1990-07-12 | 1990-07-12 | 바이폴라 소자의 메몰층 형성방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019900010597A KR930004121B1 (ko) | 1990-07-12 | 1990-07-12 | 바이폴라 소자의 메몰층 형성방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR920003448A true KR920003448A (ko) | 1992-02-29 |
KR930004121B1 KR930004121B1 (ko) | 1993-05-20 |
Family
ID=19301194
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019900010597A KR930004121B1 (ko) | 1990-07-12 | 1990-07-12 | 바이폴라 소자의 메몰층 형성방법 |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR930004121B1 (ko) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100649027B1 (ko) * | 2005-12-28 | 2006-11-27 | 동부일렉트로닉스 주식회사 | 반도체 소자의 에피택셜층 형성방법 |
-
1990
- 1990-07-12 KR KR1019900010597A patent/KR930004121B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR930004121B1 (ko) | 1993-05-20 |
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