KR910014942A - 출력회로 - Google Patents

출력회로 Download PDF

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Publication number
KR910014942A
KR910014942A KR1019910000995A KR910000995A KR910014942A KR 910014942 A KR910014942 A KR 910014942A KR 1019910000995 A KR1019910000995 A KR 1019910000995A KR 910000995 A KR910000995 A KR 910000995A KR 910014942 A KR910014942 A KR 910014942A
Authority
KR
South Korea
Prior art keywords
mos transistor
gate
source
output terminal
voltage
Prior art date
Application number
KR1019910000995A
Other languages
English (en)
Other versions
KR950006333B1 (ko
Inventor
아끼라 유모도
Original Assignee
오가 노리오
소니 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 오가 노리오, 소니 가부시끼가이샤 filed Critical 오가 노리오
Publication of KR910014942A publication Critical patent/KR910014942A/ko
Application granted granted Critical
Publication of KR950006333B1 publication Critical patent/KR950006333B1/ko

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01728—Modifications for accelerating switching in field-effect transistor circuits in synchronous circuits, i.e. by using clock signals
    • H03K19/01742—Modifications for accelerating switching in field-effect transistor circuits in synchronous circuits, i.e. by using clock signals by means of a pull-up or down element

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Dram (AREA)
  • Logic Circuits (AREA)
  • Static Random-Access Memory (AREA)

Abstract

내용 없음

Description

출력회로
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본원 발명의 출력회로의 일예의 회로도.

Claims (2)

  1. 전원전압선과 출력단자에 소스·드레인 접속되는 제1의 MOS트랜지스터와, 접시접압선과 상기 출력단에 소스·드레인이 접속되는 제2의 MOS트랜지스터를 가진 출력단(出力段)과, 상기 출력단의 각 MOS트랜지스터의 각 게이트에 접속되어 출력데이터에 따라 이 게이트의 전압을 제어하는 제어회로와, 상기 제1의 MOS트랜지스터의 게이트전압에 따라 제어되어 상기 제2의 MOS트래지스터의 게이트에 소스가 접속되는 동시에 드레인에 소정의 전압이 부여되는 제3의 MOS트랜지스터와, 상기 제2의 MOS트랜지스터의 게이트 전압에 따라 제어되어 상기 제1의 MOS트렌지스터의 게이트에 소스가 접속되는 동시에 드레인에 소정의 전압이 부여되는 제4의 MOS트랜지스터를 가지는 것을 특징으로 하는 출력회로.
  2. 제1항에 있어서, 상기 제3의 MOS트랜지스터와 상기 제4의 MOS트랜지스터는 같은 도전형의 채널을 가지는 것을 특징으로 하는 출력회로.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019910000995A 1990-01-24 1991-01-22 출력회로 KR950006333B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP90-14061 1990-01-24
JP2014061A JPH03219495A (ja) 1990-01-24 1990-01-24 出力回路

Publications (2)

Publication Number Publication Date
KR910014942A true KR910014942A (ko) 1991-08-31
KR950006333B1 KR950006333B1 (ko) 1995-06-14

Family

ID=11850576

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910000995A KR950006333B1 (ko) 1990-01-24 1991-01-22 출력회로

Country Status (5)

Country Link
US (1) US5132574A (ko)
EP (1) EP0439407B1 (ko)
JP (1) JPH03219495A (ko)
KR (1) KR950006333B1 (ko)
DE (1) DE69120097T2 (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101274701B1 (ko) * 2007-03-20 2013-06-12 엘지디스플레이 주식회사 트랜지스터의 전압 대 전류 비 측정방법

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5304874A (en) * 1991-05-31 1994-04-19 Thunderbird Technologies, Inc. Differential latching inverter and random access memory using same
KR940008718B1 (ko) * 1991-10-25 1994-09-26 삼성전자 주식회사 직류 전류를 제거한 데이타 출력버퍼
US5347183A (en) * 1992-10-05 1994-09-13 Cypress Semiconductor Corporation Sense amplifier with limited output voltage swing and cross-coupled tail device feedback
DE4400872A1 (de) * 1994-01-14 1995-07-20 Philips Patentverwaltung Ausgangstreiberschaltung
KR960013859B1 (ko) * 1994-02-07 1996-10-10 현대전자산업 주식회사 반도체 소자의 데이타 출력버퍼
JPH0883491A (ja) * 1994-09-13 1996-03-26 Mitsubishi Denki Eng Kk データ読出回路
KR100238247B1 (ko) * 1997-05-16 2000-01-15 윤종용 고속 저전력 신호라인 드라이버 및 이를 이용한 반도체메모리장치
US5963060A (en) * 1997-10-07 1999-10-05 Intel Corporation Latching sense amplifier

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4144590A (en) * 1976-12-29 1979-03-13 Texas Instruments Incorporated Intermediate output buffer circuit for semiconductor memory device
JPS56101694A (en) * 1980-01-18 1981-08-14 Nec Corp Semiconductor circuit
JPS5942690A (ja) * 1982-09-03 1984-03-09 Toshiba Corp 半導体記憶装置
JPS59181829A (ja) * 1983-03-31 1984-10-16 Toshiba Corp 半導体素子の出力バツフア回路
EP0136486A2 (en) * 1983-09-06 1985-04-10 Motorola, Inc. Latching output buffer
JPH0817037B2 (ja) * 1987-12-03 1996-02-21 松下電子工業株式会社 スタティックｒａｍの出力回路

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101274701B1 (ko) * 2007-03-20 2013-06-12 엘지디스플레이 주식회사 트랜지스터의 전압 대 전류 비 측정방법

Also Published As

Publication number Publication date
KR950006333B1 (ko) 1995-06-14
JPH03219495A (ja) 1991-09-26
EP0439407A3 (en) 1992-11-19
EP0439407B1 (en) 1996-06-12
DE69120097T2 (de) 1996-11-28
EP0439407A2 (en) 1991-07-31
US5132574A (en) 1992-07-21
DE69120097D1 (de) 1996-07-18

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