KR910003781A - 선택적으로 도핑된 헤테로 구조를 갖는 반도체 장치 - Google Patents

선택적으로 도핑된 헤테로 구조를 갖는 반도체 장치 Download PDF

Info

Publication number
KR910003781A
KR910003781A KR1019900010569A KR900010569A KR910003781A KR 910003781 A KR910003781 A KR 910003781A KR 1019900010569 A KR1019900010569 A KR 1019900010569A KR 900010569 A KR900010569 A KR 900010569A KR 910003781 A KR910003781 A KR 910003781A
Authority
KR
South Korea
Prior art keywords
layer
carrier supply
supply layer
energy level
channel layer
Prior art date
Application number
KR1019900010569A
Other languages
English (en)
Other versions
KR930006589B1 (en
Inventor
마사히로 다끼가와
유지 아와노
Original Assignee
야마모또 다꾸마
후지쓰 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 야마모또 다꾸마, 후지쓰 가부시끼가이샤 filed Critical 야마모또 다꾸마
Publication of KR910003781A publication Critical patent/KR910003781A/ko
Application granted granted Critical
Publication of KR930006589B1 publication Critical patent/KR930006589B1/ko

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H01L29/205Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/778Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • H01L29/7783Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/778Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

내용 없음.

Description

선택적으로 도핑된 헤테로 구조를 갖는 반도체 장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제4도는 본 발명의 첫번째 재료계의 원리를 설명하기 위한 그래프,
제5도는 첫번째 재료계를 기초로 구성한 본 발명에 사용된 선택적으로 도핑된 헤테로 구조의 예를 도시한 절단 측면도,
제6도는 본 발명의 두번째 재료계의 원리를 설명하기 위한 그래프.

Claims (5)

  1. 반도체 장치에 있어서, 상부 표면을 갖는 반도체 기판(11) : 반도체 기판의 상부 표면위에 제공되는 정상부 표면을 갖는 도핑되지 않은 반도체 재료의 채널층(12) : 캐리어 공급층에 대한 채널층의 상부 표면상에 제공되는 상부 표면을 갖는 도핑된 반도체 재료의 캐리어 공급층(13), 헤테로접합 인터페이스를 따라 채널층에 형성된 2차원 전자 가스(12b)로 이루어진 캐리어 공급층과 채널층 사이의 경계에서 헤테로접합 인터페이스(12a)를 형성하는 상기 캐리어공급층과 상기 채널층 : 캐리어 공급층을 통하여 2차원 전자가스로 캐리어를 주입하기 위한 캐리어 공급층의 상부 표면상에 제공된 첫번째 전극(15) : 2차원 전자가스로부터 2차원 전자가스를 통하여 흐르고 첫번째 전극을 통하여 주입된 캐리어들을 모으기 위한 첫번째 전극으로부터 분리된 캐리어 공급층의 상부표면상에 제공된 두번째 전극(16) : 2차원 전자가스를 따라 흐르고 첫번째 전극을 통하여 주입된 캐리어들의 흐름을 제어하기 위한 첫번째 전극과 두번째 전극 사이에서 캐리어 공급층의 상부 표면상에 제공된 제어전극 수단(18)으로 이루어지고, 상기 도핑된 반도체 재료가 캐리어 공급층을 형성하고 상기 도핑되지 않은 반도체 재료가 각각 결정된 조성물을 갖는 채널층을 형성하므로 캐리어 공급층의 전도대의대가 헤테로 접합 인터페이스에서 채널층의 전도대의대의 대응 에너지 레벨보다 높은 에너지레벨을 갖고, 캐리어 공급층의 전도대의 L대가 헤테로구조 인터페이스에서 채널층의 전도대의 L대의 대응 에너지레벨보다 높은 에너지 레벨을 갖고, 캐리어공급층의 전도대의 X대가 헤테로접합 인터페이스에서 전도대의 X대의 대응 에너지 레벨보다 높은 에너지 레벨을 갖고, 캐리어 공급층의 전도대의대의 에너지 레벨이 헤테로접합 인터페이스에서 채널층의 전도대의 L대의 에너지레벨보다 크거나 같고, 캐리어 공급층의 전도대의 L대의 에너지 레벨이 헤테로접합 인터페이스에서 채널층의 전도대의 X대의 에너지 레벨보다 크거나 같은 것을 특징으로 하는 선태적으로 도핑된 헤테로구조를 갖는 반도체 장치.
  2. 청구범위 제1항에 있어서, 상기 도핑된 반도체 재료가 0.56보다 크거나 같도록 선택된 조성물 X와 함께 In1-xGaXP로 표시되는 조성물을 갖는 갈리움 인듐 포스핀으로 이루어진 캐리어 공급층(13)과 칼리움 아르센티드로 이루어진 채널층을 형성하는 것을 특징으로 하는 반도체 장치.
  3. 청구범위 제1항에 있어서, 상기 캐리어 공급층이 상기 도핑된 반도체 재료의 첫번째층(13)과 상기 첫번째층 위에서 성장된 두번째층(13a)으로 이루어지고, 상기 두번째층이 캐리어 공급층과 채널층 사이에서 결정격자의 조합을 설치하도록 결정된 조성물을 갖는 것을 특징으로 하는 반도체 장치.
  4. 청구범위 제3항에 있어서, 상기 두번째 층(13)이 In0.484Ga0.516P의 조성물을 갖는 것을 특징으로 하는 반도체 장치.
  5. 청구범위 제1항에 있어서, 상기 도핑된 반도체 재료가 0.35보다 크거나 같도록 선택된 조성물과 함께 A1XGa1-As0.48xSb0.52의 조성물을 갖는 알루미늄 갈리움 아르센니드 아티모니드로 이루어진 캐리어공급층(13)과 인듐 포스핀으로 격자조합된 Ga0.53In0.47As로 이루어진 채널층을 형성하는 것을 특징으로 하는 반도체 장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR9010569A 1989-07-12 1990-07-12 Semiconductor device having a selectively doped heterostructure KR930006589B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP1178070A JP2539268B2 (ja) 1989-07-12 1989-07-12 半導体装置
JP1-178070 1989-07-12

Publications (2)

Publication Number Publication Date
KR910003781A true KR910003781A (ko) 1991-02-28
KR930006589B1 KR930006589B1 (en) 1993-07-21

Family

ID=16042091

Family Applications (1)

Application Number Title Priority Date Filing Date
KR9010569A KR930006589B1 (en) 1989-07-12 1990-07-12 Semiconductor device having a selectively doped heterostructure

Country Status (5)

Country Link
US (1) US5148245A (ko)
EP (1) EP0408001B1 (ko)
JP (1) JP2539268B2 (ko)
KR (1) KR930006589B1 (ko)
DE (1) DE69006405D1 (ko)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3086748B2 (ja) * 1991-07-26 2000-09-11 株式会社東芝 高電子移動度トランジスタ
JPH0815214B2 (ja) * 1993-03-12 1996-02-14 日本電気株式会社 量子細線構造
US6462361B1 (en) 1995-12-27 2002-10-08 Showa Denko K.K. GaInP epitaxial stacking structure and fabrication method thereof, and a FET transistor using this structure
JP3159198B2 (ja) * 1999-02-19 2001-04-23 住友電気工業株式会社 電界効果トランジスタ
TW522574B (en) * 1999-09-28 2003-03-01 Showa Denko Kk GaInP epitaxial stacking structure, a GaInP epitaxial stacking structure for FETs and a fabrication method thereof
FI20041213A0 (fi) * 2004-09-17 2004-09-17 Optogan Oy Puolijohdeheterorakenne
JP5551790B2 (ja) * 2009-12-03 2014-07-16 エプコス アクチエンゲゼルシャフト 横方向のエミッタおよびコレクタを有するバイポーラトランジスタならびに製造方法
CN106783619A (zh) * 2016-11-29 2017-05-31 东莞市广信知识产权服务有限公司 一种GaAs基PMOS器件制作方法
CN106784003A (zh) * 2016-11-29 2017-05-31 东莞市广信知识产权服务有限公司 一种GaAs基PMOS界面结构
JP7543773B2 (ja) * 2020-08-25 2024-09-03 富士通株式会社 半導体装置及びその製造方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0732247B2 (ja) * 1983-10-19 1995-04-10 富士通株式会社 半導体装置
JPS60117677A (ja) * 1983-11-30 1985-06-25 Fujitsu Ltd ヘテロ接合電界効果半導体装置
JPS60144979A (ja) * 1984-01-07 1985-07-31 Agency Of Ind Science & Technol 半導体デバイス
JP2578745B2 (ja) * 1984-10-17 1997-02-05 日本電気株式会社 電界効果トランジスタ
JPH0654786B2 (ja) * 1984-12-27 1994-07-20 住友電気工業株式会社 ヘテロ接合半導体デバイス
JPS62252975A (ja) * 1985-09-12 1987-11-04 Toshiba Corp 半導体ヘテロ接合電界効果トランジスタ
JPS62211964A (ja) * 1986-03-13 1987-09-17 Nippon Telegr & Teleph Corp <Ntt> 半導体装置
JPS6450570A (en) * 1987-08-21 1989-02-27 Fujitsu Ltd Semiconductor device

Also Published As

Publication number Publication date
EP0408001A3 (en) 1991-04-17
JPH0344038A (ja) 1991-02-25
KR930006589B1 (en) 1993-07-21
JP2539268B2 (ja) 1996-10-02
US5148245A (en) 1992-09-15
EP0408001A2 (en) 1991-01-16
EP0408001B1 (en) 1994-02-02
DE69006405D1 (de) 1994-03-17

Similar Documents

Publication Publication Date Title
US4727403A (en) Double heterojunction semiconductor device with injector
Rosenberg et al. An In0. 15 Ga0. 85 As/GaAs Pseudomorphic Single Quantum Well HEMT
KR940008230B1 (ko) 헤테로 접합 전계 효과 트랜지스터
EP0067276B1 (en) Transistor with tunnel emitter and upper energy valley base
KR950006963A (ko) 반도체 결정적층체 및 그의 형성방법과 반도체장치
KR910003781A (ko) 선택적으로 도핑된 헤테로 구조를 갖는 반도체 장치
US4878095A (en) Semiconductor device in particular a hot electron transistor
KR910016060A (ko) 화합물 반도체기판 및 그 제조방법
KR960701482A (ko) 피(p)형 II-VI족 반도체의 경사형 조성의 오믹 접촉(GRADED COMPOSITION OHMIC CONTACT FOR P-TYPE II-IV SEMICONDUCTORS)
KR930003436A (ko) 이질접합 계면을 가지며, 캐리어를 고속으로 운송하는 반도체 장치
JPS5723292A (en) Semiconductor laser device and manufacture thereof
US4371884A (en) InAs-GaSb Tunnel diode
KR950003946B1 (ko) 전계효과트랜지스터
JPS5753927A (en) Compound semiconductor device
EP0200933A1 (en) Heterojunction transistor having bipolar characteristics
US4772932A (en) Bipolar transistor and including gas layers between the emitter and base and the base and collector
Weimann et al. Carrier concentration in modulation-doped AlGaAs-GaAs heterostructures
JP2796113B2 (ja) 半導体装置
Kurobe et al. Wave function deformation and mobility of a two‐dimensional electron gas in a backgated GaAs‐AlGaAs heterostructure
JPS6235678A (ja) ダブル・ヘテロ型電界効果トランジスタ
JPS63155772A (ja) 電界効果トランジスタ
JPS6276565A (ja) 電界効果型トランジスタ
KR890017834A (ko) 반도체 레이저 및 그 제조방법
JPS6235677A (ja) 反転型高電子移動度トランジスタ装置
JPS6035577A (ja) 電界効果型トランジスタ

Legal Events

Date Code Title Description
A201 Request for examination
G160 Decision to publish patent application
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20080701

Year of fee payment: 16

LAPS Lapse due to unpaid annual fee