KR900017095A - 반도체장치의 실리사이드 형성방법 - Google Patents

반도체장치의 실리사이드 형성방법 Download PDF

Info

Publication number
KR900017095A
KR900017095A KR1019890004350A KR890004350A KR900017095A KR 900017095 A KR900017095 A KR 900017095A KR 1019890004350 A KR1019890004350 A KR 1019890004350A KR 890004350 A KR890004350 A KR 890004350A KR 900017095 A KR900017095 A KR 900017095A
Authority
KR
South Korea
Prior art keywords
polycrystalline silicon
silicide
formation method
semiconductor device
silicide formation
Prior art date
Application number
KR1019890004350A
Other languages
English (en)
Other versions
KR920010062B1 (ko
Inventor
김재갑
Original Assignee
정몽헌
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 정몽헌, 현대전자산업 주식회사 filed Critical 정몽헌
Priority to KR1019890004350A priority Critical patent/KR920010062B1/ko
Priority to US07/502,844 priority patent/US5081066A/en
Priority to JP2090040A priority patent/JPH02285632A/ja
Publication of KR900017095A publication Critical patent/KR900017095A/ko
Application granted granted Critical
Publication of KR920010062B1 publication Critical patent/KR920010062B1/ko

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28052Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/019Contacts of silicides

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

내용 없음.

Description

반도체 장치의 실리사이드 형성방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 따라 실리콘 기판 상부에 게이트 산화막, 도프된 폴리 실리콘 및 도프안된 폴리 실리콘을 순차로 적층한 상태의 단면도.
제2도는 본 발명에 따라 게이트 전극을 형성한 후 전체적으로 산화막을 형성한 상태의 단면도.
제3도는 본 발명에 따라 게이트 전극 양측면에 산화막 스페이서를 형성한 상태의 단면도.

Claims (2)

  1. 전도물질을 다결정 실리콘위에 실리사이드가 형성된 2층 구조를 만들기 위해 다결정 실리콘 위에 금속을 증착시킨후 열처리 공정에 의해 금속과 다결정 실리콘을 반응시켜 실리사이드를 형성하는데 있어서, 실리사이드막의 균일한 두께 및 표면상태를 만들기 위해 다결정 실리콘을 형성하는 단계에서 도프된 다결정 실리콘을 형성하고 그 상부에 도프안된 다결정 실리콘 형성한다음, 금속막을 상기 도프안된 다결정 실리콘 상부에 형성한후 열처리 공정에 의해 상기 금속막이 도프안된 다결정 실리콘과 반응하여 실리사이드를 형성하는 것을 특징으로 하는반도체장치의 실리사이드 형성방법.
  2. 제1항에 있어서, 상기 실리사이드 형성방법은 MOSFET의 게이트 전극 상부에서 적용되는 것을 포함하는것을 특징으로 하는 반도체장치의 실리사이드 형성방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019890004350A 1989-04-03 1989-04-03 반도체 장치의 실리사이드 형성방법 KR920010062B1 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019890004350A KR920010062B1 (ko) 1989-04-03 1989-04-03 반도체 장치의 실리사이드 형성방법
US07/502,844 US5081066A (en) 1989-04-03 1990-04-02 Method for forming a silicide film used in a semiconductor chip
JP2090040A JPH02285632A (ja) 1989-04-03 1990-04-03 半導体装置の伝導物質層の上部にシリサイド膜を形成する方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019890004350A KR920010062B1 (ko) 1989-04-03 1989-04-03 반도체 장치의 실리사이드 형성방법

Publications (2)

Publication Number Publication Date
KR900017095A true KR900017095A (ko) 1990-11-15
KR920010062B1 KR920010062B1 (ko) 1992-11-13

Family

ID=19285045

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890004350A KR920010062B1 (ko) 1989-04-03 1989-04-03 반도체 장치의 실리사이드 형성방법

Country Status (3)

Country Link
US (1) US5081066A (ko)
JP (1) JPH02285632A (ko)
KR (1) KR920010062B1 (ko)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5217923A (en) * 1989-02-13 1993-06-08 Kabushiki Kaisha Toshiba Method of fabricating a semiconductor device having silicided source/drain regions
US5252502A (en) * 1992-08-03 1993-10-12 Texas Instruments Incorporated Method of making MOS VLSI semiconductor device with metal gate
US5563093A (en) * 1993-01-28 1996-10-08 Kawasaki Steel Corporation Method of manufacturing fet semiconductor devices with polysilicon gate having large grain sizes
KR0135166B1 (ko) * 1993-07-20 1998-04-25 문정환 반도체장치의 게이트 형성방법
US5521108A (en) * 1993-09-15 1996-05-28 Lsi Logic Corporation Process for making a conductive germanium/silicon member with a roughened surface thereon suitable for use in an integrated circuit structure
JPH07297400A (ja) * 1994-03-01 1995-11-10 Hitachi Ltd 半導体集積回路装置の製造方法およびそれにより得られた半導体集積回路装置
US5498558A (en) * 1994-05-06 1996-03-12 Lsi Logic Corporation Integrated circuit structure having floating electrode with discontinuous phase of metal silicide formed on a surface thereof and process for making same
US5650654A (en) * 1994-12-30 1997-07-22 International Business Machines Corporation MOSFET device having controlled parasitic isolation threshold voltage
KR100190757B1 (ko) * 1995-06-30 1999-06-01 김영환 모스 전계 효과 트랜지스터 형성방법
US5849629A (en) * 1995-10-31 1998-12-15 International Business Machines Corporation Method of forming a low stress polycide conductors on a semiconductor chip
GB2322733A (en) * 1997-02-27 1998-09-02 Nec Corp Polysilicon electrodes for DRAM cells
US6406952B2 (en) * 1997-07-14 2002-06-18 Agere Systems Guardian Corp. Process for device fabrication
US6566181B2 (en) 1999-02-26 2003-05-20 Agere Systems Inc. Process for the fabrication of dual gate structures for CMOS devices
US6635556B1 (en) * 2001-05-17 2003-10-21 Matrix Semiconductor, Inc. Method of preventing autodoping
US7067850B2 (en) * 2001-10-16 2006-06-27 Midwest Research Institute Stacked switchable element and diode combination
US8203154B2 (en) * 2001-10-16 2012-06-19 Alliance For Sustainable Energy, Llc Stacked switchable element and diode combination with a low breakdown switchable element
US20080042191A1 (en) * 2006-08-21 2008-02-21 Macronix International Co., Ltd. Non-volatile memory device and method of fabricating the same

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4305200A (en) * 1979-11-06 1981-12-15 Hewlett-Packard Company Method of forming self-registering source, drain, and gate contacts for FET transistor structures
US4625391A (en) * 1981-06-23 1986-12-02 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor device and method for manufacturing the same
JPS584924A (ja) * 1981-07-01 1983-01-12 Hitachi Ltd 半導体装置の電極形成方法
JPS58154228A (ja) * 1982-03-09 1983-09-13 Fujitsu Ltd 半導体装置の製造方法
US4504521A (en) * 1984-03-22 1985-03-12 Rca Corporation LPCVD Deposition of tantalum silicide
JPS6213076A (ja) * 1985-07-10 1987-01-21 Mitsubishi Electric Corp 半導体装置の製造方法
JPS6255928A (ja) * 1985-09-05 1987-03-11 Fujitsu Ltd 半導体装置の製造方法
US4737474A (en) * 1986-11-17 1988-04-12 Spectrum Cvd, Inc. Silicide to silicon bonding process
US4873205A (en) * 1987-12-21 1989-10-10 International Business Machines Corporation Method for providing silicide bridge contact between silicon regions separated by a thin dielectric
US4966868A (en) * 1988-05-16 1990-10-30 Intel Corporation Process for selective contact hole filling including a silicide plug
US5001082A (en) * 1989-04-12 1991-03-19 Mcnc Self-aligned salicide process for forming semiconductor devices and devices formed thereby
US4992391A (en) * 1989-11-29 1991-02-12 Advanced Micro Devices, Inc. Process for fabricating a control gate for a floating gate FET

Also Published As

Publication number Publication date
KR920010062B1 (ko) 1992-11-13
US5081066A (en) 1992-01-14
JPH02285632A (ja) 1990-11-22

Similar Documents

Publication Publication Date Title
KR900017095A (ko) 반도체장치의 실리사이드 형성방법
KR970003718A (ko) 모스 전계 효과 트랜지스터 형성 방법
KR920022372A (ko) 게이트와 드레인이 중첩된 모오스 트랜지스터의 제조방법 및 그 구조
KR890005840A (ko) 저항성 접촉을 갖는 반도체 장치의 제조방법
KR910001762A (ko) 디램셀의 제조방법
KR970054416A (ko) 모스 전계효과 트랜지스터의 제조방법
KR930001488A (ko) Mos 장치 및 그 제조방법
KR920007221A (ko) 스태틱램의 제조방법
KR920015572A (ko) 반도체 장치의 제조방법
KR920020674A (ko) 반도체 장치 및 그 제조방법
KR960039207A (ko) 반도체 소자의 게이트 전극 제조방법
KR970054387A (ko) 모스트랜지스터 제조 방법
KR920022555A (ko) 반도체 장치의 제조방법
JPS6417475A (en) Manufacture of mos semiconductor device
KR950015658A (ko) 반도체소자 제조방법
KR970003720A (ko) 모스 전계 효과 트랜지스터의 제조방법
KR970054171A (ko) 액세스(Access) 트랜지스터에 대한 드라이브(Driver) 트랜지스터의 셀 비율 증대 방법
KR970067695A (ko) 층간 절연막 형성방법
KR960043288A (ko) 반도체 박막트렌지스터(tft)와 그 형성방법
KR950012645A (ko) 반도체 장치의 박막 트랜지스터 제조방법
KR900002472A (ko) 반도체 디바이스
KR920016611A (ko) 금속실리사이드 보호층 제조방법
KR940016740A (ko) 모스펫트(mosfet) 제조방법
KR970003984A (ko) 반도체 소자의 제조 방법
KR960026921A (ko) 게이트 전극 형성 방법

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20021018

Year of fee payment: 11

LAPS Lapse due to unpaid annual fee