KR900008332A - 레지스트 마스크 패턴 형성방법 - Google Patents
레지스트 마스크 패턴 형성방법 Download PDFInfo
- Publication number
- KR900008332A KR900008332A KR1019890015979A KR890015979A KR900008332A KR 900008332 A KR900008332 A KR 900008332A KR 1019890015979 A KR1019890015979 A KR 1019890015979A KR 890015979 A KR890015979 A KR 890015979A KR 900008332 A KR900008332 A KR 900008332A
- Authority
- KR
- South Korea
- Prior art keywords
- gas
- compound gas
- etching
- mask pattern
- forming
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/26—Processing photosensitive materials; Apparatus therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
Abstract
내용 없음.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1A∼1D도는 식각될 층과 그 위에 3층 레지스트법에 의해 여러단계로 형성한 3층 구조의 개략 단면도,
제3A∼3D도는 식각될 층과 그위에 2층 레지스터법에 의해 여러단계로 형성한 2층 구조의 개략 단면도.
Claims (13)
- 식각될 증상의 유기재질로된 레지스트층을 형성하는 단계와, 플라즈마 상태하에서 산소가스의 식각가스를 사용하여 상기 레지스터층을 선택적으로 식각하는 단계를 포함하는 레지스트 마스크 패턴 형성방법에 있어서, 상기 식각가스에 B,Si,Ti,Al,Mo, W 및 S로 구성되는 그룹으로부터 선택된 하나 이상의 원소로된 화합물 가스를 첨가하는 것이 특징인 레지스트 마스크 패턴 형성방법.
- 제1항에서, 상기 레지스트층은 다층 레지스트을 사용한 평면화 하부층인 것이 특징인 레지스트 마스코 패턴 형성 방법.
- 제1항에서, 산소가스와 화합물가스의 합계에 대한 화합물 가스의 비는 2∼50%인 것이 특징인 레지스트 마스크 패턴 형성방법.
- 제1항에서, 산소가스와 화합물가스의 합계에 대해 1-20%의 수증기;가 식각가스에 첨가되는 것이 특징인 레지스트 마스크 패턴 형성방법.
- 제1항에서, 상기 화합물 가스는 BCℓ3, BH3. B2H6, BF3및 BBr3으로 구성되는그룹으로부터 선택된 적어도 하나의 브론화합물 가스인 것이 특징인 레지스트 마스크 패턴 형성방법.
- 제1항에서, 상기 화합물 가스는 TiCℓ4,, AℓCℓ3, AℓBr3, Aℓl3, MoCℓ3및 WF6구성되는 그룹으로부터 선택된 하나 이상의 금속화합물 가스인 것이 특징인 레지스트 마스크 패턴 형성방법.
- 제1항에서, 상기 화합물 가스는 SO2, S2Cℓ2및 SCℓ2로 구성되는 그룹으로부터 선택된 하나 이상의 황화합물 가스인 것이 특징인 레지스트 마스크 패턴 형성방법.
- 제1항에서, 상기 화합물 가스 SiF4SiCℓ4및 SiBr4로 구성되는 그룹으로부터 선택된 하나 이상의 실리콘 할로겐화물 가스인 것이 특징인 레지스트 마스크 패턴 형성방법.
- 제1항에서, 상기 건식 식각단계는 반응이온식각법에 의해 수행되는 것이 특징인 레지스트 마스크 패턴 형성방법.
- 제8항에서, 상기 반응이온 식각법은 0. 01∼0.2Torr의 식각가스압, -50∼100℃의 기판온도 및 1∼3W/cm3의 파워밀도로 수행되는 것이 특징인 레지스트 마스크 패턴 형성방법.
- 제1항에서, 상기 건식식각단계는 전자 사이클로트론 공진플라즈마 식각법으로 수행되는 것이 특징인 레지스트 마스크 패턴 형성방법.
- 제10항에서, 상기 전자 사이클로트론 공진플라즈마 식각법은 1.0×10-3∼1.0×10-2Torr의 식각가스압, -5∼100℃의 기판온도, 0.2∼1.0KW의 마이크로웨이브파워 및 -100∼-400V의 바이어스 전압 조건에서 수행되는 것이 특징인 레지스트 마스트 패턴 형성방법.
- 제1항의 방법에 따라 레지스트 마스크 패턴을 형성하는 것이 특징인 레지스트 마스크 패턴으로 피복된 층을 선택적으로 식각하는 방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP01-152309 | 1988-06-16 | ||
JP63279612A JPH02125611A (ja) | 1988-11-04 | 1988-11-04 | レジストパターンの形成方法 |
JP63-279612 | 1988-11-04 | ||
JP4437089A JP2610337B2 (ja) | 1989-02-25 | 1989-02-25 | パターン形成方法 |
JP01-044370 | 1989-02-25 | ||
JP1152309A JPH0319335A (ja) | 1989-06-16 | 1989-06-16 | パターン形成方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR900008332A true KR900008332A (ko) | 1990-06-04 |
KR960007635B1 KR960007635B1 (en) | 1996-06-07 |
Family
ID=27291869
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR89015979A KR960007635B1 (en) | 1988-11-04 | 1989-11-04 | Forming method of photoresist mask pattern |
Country Status (4)
Country | Link |
---|---|
US (1) | US5447598A (ko) |
EP (1) | EP0368732B1 (ko) |
KR (1) | KR960007635B1 (ko) |
DE (1) | DE68923247T2 (ko) |
Cited By (1)
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KR100433462B1 (ko) * | 2001-03-02 | 2004-05-31 | 엔이씨 엘씨디 테크놀로지스, 엘티디. | 패턴형성방법 및 이 패턴형성방법을 이용한액정표시장치의 제조방법 |
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KR102327084B1 (ko) | 2015-07-30 | 2021-11-17 | 삼성디스플레이 주식회사 | 디스플레이 장치의 제조 방법 |
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-
1989
- 1989-11-03 DE DE68923247T patent/DE68923247T2/de not_active Expired - Fee Related
- 1989-11-03 EP EP89403039A patent/EP0368732B1/en not_active Expired - Lifetime
- 1989-11-04 KR KR89015979A patent/KR960007635B1/ko not_active IP Right Cessation
-
1993
- 1993-08-19 US US08/109,108 patent/US5447598A/en not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100433462B1 (ko) * | 2001-03-02 | 2004-05-31 | 엔이씨 엘씨디 테크놀로지스, 엘티디. | 패턴형성방법 및 이 패턴형성방법을 이용한액정표시장치의 제조방법 |
Also Published As
Publication number | Publication date |
---|---|
DE68923247T2 (de) | 1995-10-26 |
KR960007635B1 (en) | 1996-06-07 |
EP0368732A1 (en) | 1990-05-16 |
EP0368732B1 (en) | 1995-06-28 |
US5447598A (en) | 1995-09-05 |
DE68923247D1 (de) | 1995-08-03 |
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