KR900008332A - 레지스트 마스크 패턴 형성방법 - Google Patents

레지스트 마스크 패턴 형성방법 Download PDF

Info

Publication number
KR900008332A
KR900008332A KR1019890015979A KR890015979A KR900008332A KR 900008332 A KR900008332 A KR 900008332A KR 1019890015979 A KR1019890015979 A KR 1019890015979A KR 890015979 A KR890015979 A KR 890015979A KR 900008332 A KR900008332 A KR 900008332A
Authority
KR
South Korea
Prior art keywords
gas
compound gas
etching
mask pattern
forming
Prior art date
Application number
KR1019890015979A
Other languages
English (en)
Other versions
KR960007635B1 (en
Inventor
사또루 미하라
고우지 노자끼
유까리 미하라
Original Assignee
야마모도 다꾸마
후지쓰 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP63279612A external-priority patent/JPH02125611A/ja
Priority claimed from JP4437089A external-priority patent/JP2610337B2/ja
Priority claimed from JP1152309A external-priority patent/JPH0319335A/ja
Application filed by 야마모도 다꾸마, 후지쓰 가부시끼가이샤 filed Critical 야마모도 다꾸마
Publication of KR900008332A publication Critical patent/KR900008332A/ko
Application granted granted Critical
Publication of KR960007635B1 publication Critical patent/KR960007635B1/ko

Links

Classifications

    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26Processing photosensitive materials; Apparatus therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31127Etching organic layers
    • H01L21/31133Etching organic layers by chemical means
    • H01L21/31138Etching organic layers by chemical means by dry-etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers

Abstract

내용 없음.

Description

레지스트 마스크 패턴 형성방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1A∼1D도는 식각될 층과 그 위에 3층 레지스트법에 의해 여러단계로 형성한 3층 구조의 개략 단면도,
제3A∼3D도는 식각될 층과 그위에 2층 레지스터법에 의해 여러단계로 형성한 2층 구조의 개략 단면도.

Claims (13)

  1. 식각될 증상의 유기재질로된 레지스트층을 형성하는 단계와, 플라즈마 상태하에서 산소가스의 식각가스를 사용하여 상기 레지스터층을 선택적으로 식각하는 단계를 포함하는 레지스트 마스크 패턴 형성방법에 있어서, 상기 식각가스에 B,Si,Ti,Al,Mo, W 및 S로 구성되는 그룹으로부터 선택된 하나 이상의 원소로된 화합물 가스를 첨가하는 것이 특징인 레지스트 마스크 패턴 형성방법.
  2. 제1항에서, 상기 레지스트층은 다층 레지스트을 사용한 평면화 하부층인 것이 특징인 레지스트 마스코 패턴 형성 방법.
  3. 제1항에서, 산소가스와 화합물가스의 합계에 대한 화합물 가스의 비는 2∼50%인 것이 특징인 레지스트 마스크 패턴 형성방법.
  4. 제1항에서, 산소가스와 화합물가스의 합계에 대해 1-20%의 수증기;가 식각가스에 첨가되는 것이 특징인 레지스트 마스크 패턴 형성방법.
  5. 제1항에서, 상기 화합물 가스는 BCℓ3, BH3. B2H6, BF3및 BBr3으로 구성되는그룹으로부터 선택된 적어도 하나의 브론화합물 가스인 것이 특징인 레지스트 마스크 패턴 형성방법.
  6. 제1항에서, 상기 화합물 가스는 TiCℓ4,, AℓCℓ3, AℓBr3, Aℓl3, MoCℓ3및 WF6구성되는 그룹으로부터 선택된 하나 이상의 금속화합물 가스인 것이 특징인 레지스트 마스크 패턴 형성방법.
  7. 제1항에서, 상기 화합물 가스는 SO2, S2Cℓ2및 SCℓ2로 구성되는 그룹으로부터 선택된 하나 이상의 황화합물 가스인 것이 특징인 레지스트 마스크 패턴 형성방법.
  8. 제1항에서, 상기 화합물 가스 SiF4SiCℓ4및 SiBr4로 구성되는 그룹으로부터 선택된 하나 이상의 실리콘 할로겐화물 가스인 것이 특징인 레지스트 마스크 패턴 형성방법.
  9. 제1항에서, 상기 건식 식각단계는 반응이온식각법에 의해 수행되는 것이 특징인 레지스트 마스크 패턴 형성방법.
  10. 제8항에서, 상기 반응이온 식각법은 0. 01∼0.2Torr의 식각가스압, -50∼100℃의 기판온도 및 1∼3W/cm3의 파워밀도로 수행되는 것이 특징인 레지스트 마스크 패턴 형성방법.
  11. 제1항에서, 상기 건식식각단계는 전자 사이클로트론 공진플라즈마 식각법으로 수행되는 것이 특징인 레지스트 마스크 패턴 형성방법.
  12. 제10항에서, 상기 전자 사이클로트론 공진플라즈마 식각법은 1.0×10-3∼1.0×10-2Torr의 식각가스압, -5∼100℃의 기판온도, 0.2∼1.0KW의 마이크로웨이브파워 및 -100∼-400V의 바이어스 전압 조건에서 수행되는 것이 특징인 레지스트 마스트 패턴 형성방법.
  13. 제1항의 방법에 따라 레지스트 마스크 패턴을 형성하는 것이 특징인 레지스트 마스크 패턴으로 피복된 층을 선택적으로 식각하는 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR89015979A 1988-11-04 1989-11-04 Forming method of photoresist mask pattern KR960007635B1 (en)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
JP01-152309 1988-06-16
JP63279612A JPH02125611A (ja) 1988-11-04 1988-11-04 レジストパターンの形成方法
JP63-279612 1988-11-04
JP4437089A JP2610337B2 (ja) 1989-02-25 1989-02-25 パターン形成方法
JP01-044370 1989-02-25
JP1152309A JPH0319335A (ja) 1989-06-16 1989-06-16 パターン形成方法

Publications (2)

Publication Number Publication Date
KR900008332A true KR900008332A (ko) 1990-06-04
KR960007635B1 KR960007635B1 (en) 1996-06-07

Family

ID=27291869

Family Applications (1)

Application Number Title Priority Date Filing Date
KR89015979A KR960007635B1 (en) 1988-11-04 1989-11-04 Forming method of photoresist mask pattern

Country Status (4)

Country Link
US (1) US5447598A (ko)
EP (1) EP0368732B1 (ko)
KR (1) KR960007635B1 (ko)
DE (1) DE68923247T2 (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100433462B1 (ko) * 2001-03-02 2004-05-31 엔이씨 엘씨디 테크놀로지스, 엘티디. 패턴형성방법 및 이 패턴형성방법을 이용한액정표시장치의 제조방법

Families Citing this family (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0336723A (ja) * 1989-07-04 1991-02-18 Fujitsu Ltd 半導体装置の製造方法及び電子サイクロトロン共鳴エッチング装置
US5082524A (en) * 1990-07-30 1992-01-21 Micron Technology, Inc. Addition of silicon tetrabromide to halogenated plasmas as a technique for minimizing photoresist deterioration during the etching of metal layers
FR2673763A1 (fr) * 1991-03-06 1992-09-11 Centre Nat Rech Scient Procede de gravure anisotrope des polymeres par plasma.
JPH0786244A (ja) * 1993-09-13 1995-03-31 Sony Corp ドライエッチング方法
JP3360461B2 (ja) * 1995-01-31 2002-12-24 ソニー株式会社 メタル成膜工程の前処理方法
US5773367A (en) * 1996-09-06 1998-06-30 Integrated Device Technology, Inc. High throughput planarization etch process for interlayer oxide films between metals and pre-metals
KR100232187B1 (ko) * 1996-12-27 1999-12-01 김영환 반사방지막 식각방법
EP0903777A4 (en) * 1997-01-21 2005-09-14 Matsushita Electric Ind Co Ltd CONFIGURATION FORMATION METHOD
DE19706682C2 (de) * 1997-02-20 1999-01-14 Bosch Gmbh Robert Anisotropes fluorbasiertes Plasmaätzverfahren für Silizium
US5930664A (en) * 1997-07-24 1999-07-27 Taiwan Semiconductor Manufacturing Company, Ltd. Process for preventing corrosion of aluminum bonding pads after passivation/ARC layer etching
US5948701A (en) * 1997-07-30 1999-09-07 Chartered Semiconductor Manufacturing, Ltd. Self-aligned contact (SAC) etching using polymer-building chemistry
US5969805A (en) 1997-11-04 1999-10-19 Micron Technology, Inc. Method and apparatus employing external light source for endpoint detection
US7102737B2 (en) * 1997-11-04 2006-09-05 Micron Technology, Inc. Method and apparatus for automated, in situ material detection using filtered fluoresced, reflected, or absorbed light
US6704107B1 (en) 1997-11-04 2004-03-09 Micron Technology, Inc. Method and apparatus for automated, in situ material detection using filtered fluoresced, reflected, or absorbed light
EP1074043A4 (en) * 1998-01-28 2002-11-06 Anon Inc METHOD OF BURNING ORGANIC MATERIALS PRESENT ON THE SURFACE OF SUBSTRATES
US6231775B1 (en) 1998-01-28 2001-05-15 Anon, Inc. Process for ashing organic materials from substrates
EP0997929A1 (en) * 1998-10-30 2000-05-03 Tokyo Electron Limited Plasma etching of polymer materials
US20030093894A1 (en) * 1999-02-23 2003-05-22 Dugas Matthew P. Double layer patterning and technique for making a magnetic recording head
US6269533B2 (en) * 1999-02-23 2001-08-07 Advanced Research Corporation Method of making a patterned magnetic recording head
US6544902B1 (en) 1999-02-26 2003-04-08 Micron Technology, Inc. Energy beam patterning of protective layers for semiconductor devices
US6465159B1 (en) * 1999-06-28 2002-10-15 Lam Research Corporation Method and apparatus for side wall passivation for organic etch
US6496328B1 (en) 1999-12-30 2002-12-17 Advanced Research Corporation Low inductance, ferrite sub-gap substrate structure for surface film magnetic recording heads
DE10027932C2 (de) * 2000-05-31 2003-10-02 Infineon Technologies Ag Verfahren zur Bildung eines Kontaktlochs in einer Isolierschicht eines elektronischen oder mikroelektronischen Bauelements
US6365508B1 (en) * 2000-07-18 2002-04-02 Chartered Semiconductor Manufacturing Ltd. Process without post-etch cleaning-converting polymer and by-products into an inert layer
EP1233449A3 (en) * 2001-02-15 2006-03-01 Interuniversitair Micro-Elektronica Centrum A method of fabricating a semiconductor device
US6720132B2 (en) * 2002-01-08 2004-04-13 Taiwan Semiconductor Manufacturing Co., Ltd. Bi-layer photoresist dry development and reactive ion etch method
US20040224524A1 (en) * 2003-05-09 2004-11-11 Applied Materials, Inc. Maintaining the dimensions of features being etched on a lithographic mask
US7141505B2 (en) * 2003-06-27 2006-11-28 Lam Research Corporation Method for bilayer resist plasma etch
JP4727171B2 (ja) * 2003-09-29 2011-07-20 東京エレクトロン株式会社 エッチング方法
US8144424B2 (en) 2003-12-19 2012-03-27 Dugas Matthew P Timing-based servo verify head and magnetic media made therewith
JP2007536683A (ja) 2004-05-04 2007-12-13 アドバンスト・リサーチ・コーポレーション 任意形状のギャップ・パターンのための集積型薄膜サブギャップ/サブ磁極構造、磁気記録ヘッド、及びその製造方法
US20090115027A1 (en) * 2007-11-05 2009-05-07 Stephan Wege Method of Fabricating an Integrated Circuit
JP2009200080A (ja) * 2008-02-19 2009-09-03 Tokyo Electron Ltd プラズマエッチング方法、プラズマエッチング装置、制御プログラム及びコンピュータ記憶媒体
WO2009121073A1 (en) 2008-03-28 2009-10-01 Advanced Research Corporation Thin film planar arbitrary gap pattern magnetic head
US8809195B2 (en) * 2008-10-20 2014-08-19 Asm America, Inc. Etching high-k materials
WO2011014836A2 (en) 2009-07-31 2011-02-03 Advanced Research Corporation Erase drive systems and methods of erasure for tape data cartridge
KR101994820B1 (ko) * 2012-07-26 2019-07-02 에스케이하이닉스 주식회사 실리콘함유막과 금속함유막이 적층된 반도체 구조물 및 그의 제조 방법
KR102327084B1 (ko) 2015-07-30 2021-11-17 삼성디스플레이 주식회사 디스플레이 장치의 제조 방법
US10283369B2 (en) * 2016-08-10 2019-05-07 Tokyo Electron Limited Atomic layer etching using a boron-containing gas and hydrogen fluoride gas
CN115376908A (zh) * 2022-08-26 2022-11-22 北京北方华创微电子装备有限公司 GaN衬底的刻蚀方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4303467A (en) * 1977-11-11 1981-12-01 Branson International Plasma Corporation Process and gas for treatment of semiconductor devices
GB2085482B (en) * 1980-10-06 1985-03-06 Optical Coating Laboratory Inc Forming thin film oxide layers using reactive evaporation techniques
US4462882A (en) * 1983-01-03 1984-07-31 Massachusetts Institute Of Technology Selective etching of aluminum
JPS59163826A (ja) * 1983-03-08 1984-09-14 Toshiba Corp ドライエツチング方法
US4681653A (en) * 1984-06-01 1987-07-21 Texas Instruments Incorporated Planarized dielectric deposited using plasma enhanced chemical vapor deposition
JPS6113626A (ja) * 1984-06-29 1986-01-21 Hitachi Ltd プラズマ処理装置
US4702795A (en) * 1985-05-03 1987-10-27 Texas Instruments Incorporated Trench etch process
US4613400A (en) * 1985-05-20 1986-09-23 Applied Materials, Inc. In-situ photoresist capping process for plasma etching
US4661204A (en) * 1985-10-25 1987-04-28 Tandem Computers Inc. Method for forming vertical interconnects in polyimide insulating layers

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100433462B1 (ko) * 2001-03-02 2004-05-31 엔이씨 엘씨디 테크놀로지스, 엘티디. 패턴형성방법 및 이 패턴형성방법을 이용한액정표시장치의 제조방법

Also Published As

Publication number Publication date
DE68923247T2 (de) 1995-10-26
KR960007635B1 (en) 1996-06-07
EP0368732A1 (en) 1990-05-16
EP0368732B1 (en) 1995-06-28
US5447598A (en) 1995-09-05
DE68923247D1 (de) 1995-08-03

Similar Documents

Publication Publication Date Title
KR900008332A (ko) 레지스트 마스크 패턴 형성방법
KR100592818B1 (ko) 다이아몬드와 유사한 경도를 가지며 플라즈마 증착 방법에의해 제조되는 탄소 하드 마스크 층에 의한포토리소그래피 패터닝 방법
WO2004061916B1 (en) Method of forming a low-k dual damascene interconnect structure
US20040217086A1 (en) Pattern formation method
JPH04274323A (ja) 選択的にエッチングする方法
KR860009475A (ko) 플라즈마 에칭에 관한 원지 포토레지스트의 캡핑 프로세스
US6444584B1 (en) Plasma etch method for forming composite silicon/dielectric/silicon stack layer
US7067429B2 (en) Processing method of forming MRAM circuitry
US4937643A (en) Devices having tantalum silicide structures
US6919147B2 (en) Production method for a halftone phase mask
KR930008186A (ko) 패터닝 방법
KR980005629A (ko) 폴리사이드 구조의 게이트 형성방법
TW200501321A (en) Method of manufacturing a semiconductor device and semiconductor device obtained by using such a method
US4892635A (en) Pattern transfer process utilizing multilevel resist structure for fabricating integrated-circuit devices
KR100937331B1 (ko) 반도체 소자의 층간 절연막
KR100468700B1 (ko) 반도체장치의미세패턴을형성하기위한건식식각방법
KR870011687A (ko) 반도체 집적회로의 제조공정에서 절연층 내부로 에칭된 콘택호올을 텅스텐으로 메꾸는 방법
KR19990086491A (ko) 반도체장치의 다층막 식각방법
KR100298180B1 (ko) 반도체소자의콘택홀형성방법
KR970030391A (ko) 반도체 장치의 미세 패턴 형성방법(a method of forming a fine pattern in a semiconductor device)
KR20110054970A (ko) 실리콘 카바이드 전자소자 제작을 위한 이온주입 마스크 제작 방법
KR920007067A (ko) 반도체 제조중 콘택트홀의 형성방법
KR20000003056A (ko) 실리콘 질화막을 이용한 반도체장치의 다결정 실리콘층 식각방법
KR970052372A (ko) 반도체 장치의 금속배선 형성방법
GB2170041A (en) Forming multilayer conduction tracks on a substrate

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E601 Decision to refuse application
J2X1 Appeal (before the patent court)

Free format text: APPEAL AGAINST DECISION TO DECLINE REFUSAL

G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20040524

Year of fee payment: 9

LAPS Lapse due to unpaid annual fee