KR900001395B1 - 반도체장치의 제조방법 - Google Patents

반도체장치의 제조방법 Download PDF

Info

Publication number
KR900001395B1
KR900001395B1 KR1019840006294A KR840006294A KR900001395B1 KR 900001395 B1 KR900001395 B1 KR 900001395B1 KR 1019840006294 A KR1019840006294 A KR 1019840006294A KR 840006294 A KR840006294 A KR 840006294A KR 900001395 B1 KR900001395 B1 KR 900001395B1
Authority
KR
South Korea
Prior art keywords
thin film
melting point
high melting
point metal
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
KR1019840006294A
Other languages
English (en)
Korean (ko)
Other versions
KR850005139A (ko
Inventor
다쯔오 오까모또
히토시 하라다
Original Assignee
미쯔비시 덴끼 가부시끼 가이샤
가따야마 진하찌토
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 미쯔비시 덴끼 가부시끼 가이샤, 가따야마 진하찌토 filed Critical 미쯔비시 덴끼 가부시끼 가이샤
Publication of KR850005139A publication Critical patent/KR850005139A/ko
Application granted granted Critical
Publication of KR900001395B1 publication Critical patent/KR900001395B1/ko
Expired legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/01—Manufacture or treatment
    • H10D1/045—Manufacture or treatment of capacitors having potential barriers, e.g. varactors
    • H10D1/047—Manufacture or treatment of capacitors having potential barriers, e.g. varactors of conductor-insulator-semiconductor capacitors, e.g. trench capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32105—Oxidation of silicon-containing layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/014—Capacitor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/043—Dual dielectric
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/081—Insulators
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/118—Oxide films
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/147—Silicides

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
  • Electrodes Of Semiconductors (AREA)
KR1019840006294A 1983-12-20 1984-10-11 반도체장치의 제조방법 Expired KR900001395B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP242631 1983-12-20
JP58242631A JPS60132353A (ja) 1983-12-20 1983-12-20 半導体装置の製造方法
JP58-242631 1983-12-20

Publications (2)

Publication Number Publication Date
KR850005139A KR850005139A (ko) 1985-08-21
KR900001395B1 true KR900001395B1 (ko) 1990-03-09

Family

ID=17091921

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019840006294A Expired KR900001395B1 (ko) 1983-12-20 1984-10-11 반도체장치의 제조방법

Country Status (4)

Country Link
US (1) US4665608A (enExample)
JP (1) JPS60132353A (enExample)
KR (1) KR900001395B1 (enExample)
DE (1) DE3446643A1 (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5027166A (en) * 1987-12-04 1991-06-25 Sanken Electric Co., Ltd. High voltage, high speed Schottky semiconductor device and method of fabrication
JP2569115B2 (ja) * 1988-04-15 1997-01-08 株式会社日立製作所 半導体装置
US5036020A (en) * 1990-08-31 1991-07-30 Texas Instrument Incorporated Method of fabricating microelectronic device incorporating capacitor having lowered topographical profile
US5470398A (en) * 1990-09-25 1995-11-28 Matsushita Electric Industrial Co., Ltd. Dielectric thin film and method of manufacturing same
US5206187A (en) * 1991-08-30 1993-04-27 Micron Technology, Inc. Method of processing semiconductor wafers using a contact etch stop
US5449941A (en) * 1991-10-29 1995-09-12 Semiconductor Energy Laboratory Co., Ltd. Semiconductor memory device
KR960005681B1 (ko) * 1992-11-07 1996-04-30 금성일렉트론주식회사 반도체 메모리 장치의 캐패시터 제조방법
JP2630292B2 (ja) * 1995-02-27 1997-07-16 日本電気株式会社 半導体装置の製造方法
US5593924A (en) * 1995-06-02 1997-01-14 Texas Instruments Incorporated Use of a capping layer to attain low titanium-silicide sheet resistance and uniform silicide thickness for sub-micron silicon and polysilicon lines
WO1997019468A1 (en) * 1995-11-20 1997-05-29 Hitachi, Ltd. Semiconductor storage device and process for manufacturing the same
US6660610B2 (en) * 1996-07-08 2003-12-09 Micron Technology, Inc. Devices having improved capacitance and methods of their fabrication
EP1106982B1 (de) * 1999-12-10 2005-02-09 Endress + Hauser GmbH + Co. KG Druckmessgerät

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5514531B1 (enExample) * 1969-06-18 1980-04-17
US3741880A (en) * 1969-10-25 1973-06-26 Nippon Electric Co Method of forming electrical connections in a semiconductor integrated circuit
US4158613A (en) * 1978-12-04 1979-06-19 Burroughs Corporation Method of forming a metal interconnect structure for integrated circuits
JPS5847862B2 (ja) * 1979-08-30 1983-10-25 富士通株式会社 半導体記憶装置及びその製造方法
JPS56137657A (en) * 1980-03-29 1981-10-27 Chiyou Lsi Gijutsu Kenkyu Kumiai Manufacture of semiconductor device
GB2077993A (en) * 1980-06-06 1981-12-23 Standard Microsyst Smc Low sheet resistivity composite conductor gate MOS device
US4285761A (en) * 1980-06-30 1981-08-25 International Business Machines Corporation Process for selectively forming refractory metal silicide layers on semiconductor devices
JPS5724541A (en) * 1980-07-21 1982-02-09 Nec Corp Preparation of metal oxide semiconductor
GB2083946A (en) * 1980-09-15 1982-03-31 Gen Electric Method of making integrated circuits
US4339869A (en) * 1980-09-15 1982-07-20 General Electric Company Method of making low resistance contacts in semiconductor devices by ion induced silicides
US4419142A (en) * 1980-10-24 1983-12-06 Tokyo Shibaura Denki Kabushiki Kaisha Method of forming dielectric isolation of device regions
US4403394A (en) * 1980-12-17 1983-09-13 International Business Machines Corporation Formation of bit lines for ram device
DE3132809A1 (de) * 1981-08-19 1983-03-10 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von integrierten mos-feldeffekttransistoren, insbesondere von komplementaeren mos-feldeffekttransistorenschaltungen mit einer aus metallsiliziden bestehenden zusaetzlichen leiterbahnebene
DE3211761A1 (de) * 1982-03-30 1983-10-06 Siemens Ag Verfahren zum herstellen von integrierten mos-feldeffekttransistorschaltungen in siliziumgate-technologie mit silizid beschichteten diffusionsgebieten als niederohmige leiterbahnen

Also Published As

Publication number Publication date
DE3446643C2 (enExample) 1993-05-13
JPS60132353A (ja) 1985-07-15
JPH0311552B2 (enExample) 1991-02-18
US4665608A (en) 1987-05-19
KR850005139A (ko) 1985-08-21
DE3446643A1 (de) 1985-06-27

Similar Documents

Publication Publication Date Title
US6188098B1 (en) Semiconductor device and method of manufacturing the same
US5406447A (en) Capacitor used in an integrated circuit and comprising opposing electrodes having barrier metal films in contact with a dielectric film
US4716131A (en) Method of manufacturing semiconductor device having polycrystalline silicon layer with metal silicide film
JPH05299578A (ja) 半導体装置およびその製法
KR900001395B1 (ko) 반도체장치의 제조방법
JPS60153158A (ja) キャパシタ誘電体膜の製造方法
US4322881A (en) Method for manufacturing semiconductor memory devices
KR0131186B1 (ko) 고집적 적층 캐패시터 제조방법
JP2633584B2 (ja) 半導体装置及びその製造方法
KR20000012051A (ko) 반도체 장치의 제조 방법 및 반도체 장치
KR100199093B1 (ko) 반도체 소자의 커패시터 제조방법
JPS59195870A (ja) 半導体装置
US6306666B1 (en) Method for fabricating ferroelectric memory device
JPH0645614A (ja) 読出し専用半導体メモリの製造方法
JPH06334118A (ja) 半導体装置及びその製造方法
JPH03259566A (ja) メモリ装置の製造方法
KR19990018070A (ko) 반도체 메모리장치의 캐패시터 및 그 제조방법
JPH0563157A (ja) 半導体装置
JPH10154792A (ja) 半導体集積回路とその製造方法
JPH0414862A (ja) 半導体装置
US5888895A (en) Method for making titanium poly-silicide CMOS circuit contacts
JPS60233861A (ja) 半導体装置及びその製造方法
JP2796724B2 (ja) 半導体装置の製造方法
JPS61150376A (ja) 半導体装置
GB2249217A (en) Semiconductor device planarisation

Legal Events

Date Code Title Description
PA0109 Patent application

St.27 status event code: A-0-1-A10-A12-nap-PA0109

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

A201 Request for examination
PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

G160 Decision to publish patent application
PG1605 Publication of application before grant of patent

St.27 status event code: A-2-2-Q10-Q13-nap-PG1605

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U11-oth-PR1002

Fee payment year number: 1

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 6

FPAY Annual fee payment

Payment date: 19960228

Year of fee payment: 7

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 7

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 19970310

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-PN2301

St.27 status event code: A-5-5-R10-R11-asn-PN2301

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-PN2301

St.27 status event code: A-5-5-R10-R11-asn-PN2301

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-PN2301

St.27 status event code: A-5-5-R10-R11-asn-PN2301

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 19970310

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-PN2301

St.27 status event code: A-5-5-R10-R11-asn-PN2301

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000