KR890015346A - 웨이퍼기판 및 화합물 반도체층으로 구성된 반도체기판 - Google Patents

웨이퍼기판 및 화합물 반도체층으로 구성된 반도체기판

Info

Publication number
KR890015346A
KR890015346A KR1019890002569A KR890002569A KR890015346A KR 890015346 A KR890015346 A KR 890015346A KR 1019890002569 A KR1019890002569 A KR 1019890002569A KR 890002569 A KR890002569 A KR 890002569A KR 890015346 A KR890015346 A KR 890015346A
Authority
KR
South Korea
Prior art keywords
substrate
semiconductor layer
compound semiconductor
wafer
wafer substrate
Prior art date
Application number
KR1019890002569A
Other languages
English (en)
Other versions
KR930004239B1 (ko
Inventor
히로시 오꾸다
Original Assignee
후지쓰 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 후지쓰 가부시끼가이샤 filed Critical 후지쓰 가부시끼가이샤
Publication of KR890015346A publication Critical patent/KR890015346A/ko
Application granted granted Critical
Publication of KR930004239B1 publication Critical patent/KR930004239B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/15—Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
    • H01L29/151—Compositional structures
    • H01L29/152—Compositional structures with quantum effects only in vertical direction, i.e. layered structures with quantum effects solely resulting from vertical potential variation
    • H01L29/155—Comprising only semiconductor materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02387—Group 13/15 materials
    • H01L21/02395—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02461—Phosphides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02463—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02505—Layer structure consisting of more than two layers
    • H01L21/02507—Alternating layers, e.g. superlattice
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02543—Phosphides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02546—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/26—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys
    • H01L29/267—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/16—Superlattice
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/938—Lattice strain control or utilization

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Recrystallisation Techniques (AREA)
KR1019890002569A 1988-03-01 1989-03-02 웨이퍼기판 및 화합물 반도체층으로 구성된 반도체기판 KR930004239B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP63045820A JP2649936B2 (ja) 1988-03-01 1988-03-01 歪超格子バッファ
JP88-045820 1988-03-01

Publications (2)

Publication Number Publication Date
KR890015346A true KR890015346A (ko) 1989-10-30
KR930004239B1 KR930004239B1 (ko) 1993-05-22

Family

ID=12729886

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890002569A KR930004239B1 (ko) 1988-03-01 1989-03-02 웨이퍼기판 및 화합물 반도체층으로 구성된 반도체기판

Country Status (5)

Country Link
US (1) US4927471A (ko)
EP (1) EP0331433B1 (ko)
JP (1) JP2649936B2 (ko)
KR (1) KR930004239B1 (ko)
DE (1) DE68919485T2 (ko)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06101588B2 (ja) * 1989-08-22 1994-12-12 京都大学長 半導体材料
US5021360A (en) * 1989-09-25 1991-06-04 Gte Laboratories Incorporated Method of farbicating highly lattice mismatched quantum well structures
JPH03174790A (ja) * 1989-09-26 1991-07-29 Fujitsu Ltd 光半導体素子
JPH03136319A (ja) * 1989-10-23 1991-06-11 Fujitsu Ltd ヘテロエピタキシャル基板および半導体装置
US5164359A (en) * 1990-04-20 1992-11-17 Eaton Corporation Monolithic integrated circuit having compound semiconductor layer epitaxially grown on ceramic substrate
US5225368A (en) * 1991-02-08 1993-07-06 The United States Of America As Represented By The United States Department Of Energy Method of producing strained-layer semiconductor devices via subsurface-patterning
CA2062134C (en) * 1991-05-31 1997-03-25 Ibm Heteroepitaxial layers with low defect density and arbitrary network parameter
US5523592A (en) * 1993-02-03 1996-06-04 Hitachi, Ltd. Semiconductor optical device, manufacturing method for the same, and opto-electronic integrated circuit using the same
JP3274246B2 (ja) * 1993-08-23 2002-04-15 コマツ電子金属株式会社 エピタキシャルウェーハの製造方法
US5479032A (en) * 1994-07-21 1995-12-26 Trustees Of Princeton University Multiwavelength infrared focal plane array detector
JP3888668B2 (ja) * 2000-12-28 2007-03-07 日本碍子株式会社 半導体発光素子
JP3785970B2 (ja) * 2001-09-03 2006-06-14 日本電気株式会社 Ｉｉｉ族窒化物半導体素子の製造方法
US7045836B2 (en) * 2003-07-31 2006-05-16 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure having a strained region and a method of fabricating same
US7495267B2 (en) * 2003-09-08 2009-02-24 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure having a strained region and a method of fabricating same
US8513643B2 (en) 2006-09-06 2013-08-20 Palo Alto Research Center Incorporated Mixed alloy defect redirection region and devices including same
US20080054248A1 (en) * 2006-09-06 2008-03-06 Chua Christopher L Variable period variable composition supperlattice and devices including same
EP2037506B1 (en) * 2007-09-17 2019-07-24 Palo Alto Research Center Incorporated Semiconductor light emitting device with superlattices
JP5558454B2 (ja) 2011-11-25 2014-07-23 シャープ株式会社 窒化物半導体発光素子および窒化物半導体発光素子の製造方法
US10991847B2 (en) * 2019-01-18 2021-04-27 Alliance For Sustainable Energy, Llc Semiconducting devices containing quantum wells
WO2023091693A1 (en) * 2021-11-18 2023-05-25 Meta Platforms Technologies, Llc Red light-emitting diode with phosphide epitaxial heterostructure grown on silicon

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2225207B1 (ko) * 1973-04-16 1978-04-21 Ibm
JPS6191098A (ja) * 1984-10-09 1986-05-09 Daido Steel Co Ltd シリコン基板上における砒素化ガリウム成長結晶体とその結晶成長方法
FR2595509B1 (fr) * 1986-03-07 1988-05-13 Thomson Csf Composant en materiau semiconducteur epitaxie sur un substrat a parametre de maille different et application a divers composants en semiconducteurs
US4804639A (en) * 1986-04-18 1989-02-14 Bell Communications Research, Inc. Method of making a DH laser with strained layers by MBE
US4771013A (en) * 1986-08-01 1988-09-13 Texas Instruments Incorporated Process of making a double heterojunction 3-D I2 L bipolar transistor with a Si/Ge superlattice
US4769341A (en) * 1986-12-29 1988-09-06 American Telephone And Telegraph Company, At&T Bell Laboratories Method of fabricating non-silicon materials on silicon substrate using an alloy of Sb and Group IV semiconductors
JPS63248121A (ja) * 1987-04-03 1988-10-14 Mitsubishi Electric Corp エピタキシヤル結晶成長方法

Also Published As

Publication number Publication date
EP0331433A1 (en) 1989-09-06
DE68919485T2 (de) 1995-04-06
US4927471A (en) 1990-05-22
JP2649936B2 (ja) 1997-09-03
EP0331433B1 (en) 1994-11-30
JPH01222431A (ja) 1989-09-05
KR930004239B1 (ko) 1993-05-22
DE68919485D1 (de) 1995-01-12

Similar Documents

Publication Publication Date Title
KR890015346A (ko) 웨이퍼기판 및 화합물 반도체층으로 구성된 반도체기판
DE69219268T2 (de) Planarisierung eines Halbleitersubstrates
DE69331817T2 (de) Herstellungsverfahren eines Halbleitersubstrat
KR890004408A (ko) 반도체장치 제조시에 기판상에 형성되는 레지스트층의 애슁법
KR890012373A (ko) 반도체장치의 제조방법
DE69333078D1 (de) Halbleiterwafer mit geringer Oberflächenrauhigkeit und Halbleiterbauelement
DE68927026D1 (de) Herstellungsverfahren einer Halbleitervorrichtung
KR890008951A (ko) 실리콘 카바이드 기판의 제조방법
KR860006132A (ko) 반도체 장치용 기판 구조체
KR900008660A (ko) 반도체장치의 제조방법
KR880006786A (ko) 반도체장치의 제조방법
EP0442414A3 (en) Compound semiconductor substrate and method of manufacturing the same
KR880700449A (ko) 에피텍셜층의 오토도핑 방지 방법 및 이를 이용한 반도체 소자
EP0547684A3 (en) Method of manufacturing a semiconductor body comprising a carrier wafer and a monocrystalline semiconducting top layer
KR880008418A (ko) 반도체장치의 제조방법
KR900008697A (ko) 반도체 웨이퍼 제조방법
KR900008664A (ko) 캐리어기판 및 그 제조방법
KR900011045A (ko) 반도체장치의 제조방법
EP0367292A3 (en) Compound semiconductor substrate
KR900007072A (ko) 반도체장치의 제조방법
KR890015347A (ko) 변형 초격자 구조층을 포함하는 반도체 기판
HK164695A (en) A semiconductor substrate having a superconducting thin film
EP0195236A3 (en) Semiconductor substrate bias generator
KR900008689A (ko) 반도체장치의 제조방법
KR840005918A (ko) 반도체 장치의 기판구조 및 그 제조방법

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20050511

Year of fee payment: 13

LAPS Lapse due to unpaid annual fee