KR880012009A - BiMOS 논리회로 - Google Patents

BiMOS 논리회로 Download PDF

Info

Publication number
KR880012009A
KR880012009A KR1019880003258A KR880003258A KR880012009A KR 880012009 A KR880012009 A KR 880012009A KR 1019880003258 A KR1019880003258 A KR 1019880003258A KR 880003258 A KR880003258 A KR 880003258A KR 880012009 A KR880012009 A KR 880012009A
Authority
KR
South Korea
Prior art keywords
transistor
logic circuit
gate
transistors
bimos logic
Prior art date
Application number
KR1019880003258A
Other languages
English (en)
Other versions
KR900008799B1 (ko
Inventor
마사미 마스다
다카유키 가와구치
야스미츠 노자와
Original Assignee
아오이 죠이치
가부시키가이샤 도시바
다케다이 마사다카
도시바마이콤엔지니어링 가부시키가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 아오이 죠이치, 가부시키가이샤 도시바, 다케다이 마사다카, 도시바마이콤엔지니어링 가부시키가이샤 filed Critical 아오이 죠이치
Publication of KR880012009A publication Critical patent/KR880012009A/ko
Application granted granted Critical
Publication of KR900008799B1 publication Critical patent/KR900008799B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/80—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used using non-linear magnetic devices; using non-linear dielectric devices
    • H03K17/82—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used using non-linear magnetic devices; using non-linear dielectric devices the devices being transfluxors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/09448—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET in combination with bipolar transistors [BIMOS]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals
    • H03K19/0963—Synchronous circuits, i.e. using clock signals using transistors of complementary type

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Nonlinear Science (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

내용 없음

Description

BiMOS 논리회로
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제4도는 본 발명에 관한 BiMOS 논리회로의 1실시예를 나타낸 회로도.
제5도는 본 발명의 원리가 적용된 다른 회로구성을 나타낸 회로도이다.

Claims (2)

  1. PMOS 트랜지스터로 구성되는 제1트랜지스터와, NMOS 트랜지스터로 구성되는 제2트랜지스터, 바이폴라트랜지스터로 구성되는 제3트랜지스터, NMOS 트랜지스터로 구성되는 제4트랜지스터, NMOS 트랜지스터로 구성되는 제5트랜지스터를 구비하면서, 제1트랜지스터의 일단과 제2트랜지스터의 일단이 상호 중간 접촉점에서 접속됨과 더불어 제1트랜지스터의 게이트와 제2트랜지스터의 게이트는 입력단자에 접속되고, 이 제1 및 제2트랜지스터 중 하나의 트랜지스터의 다른 단에 제1전원전압이 인가됨과 더불어 다른 트랜지스터의 다른 단에 제어신호가 인가되며, 제3트랜지스터의 베이스가 상기 중간 접속점에 접속되면서 이 제3트랜지스터의 컬렉터 또는 에미터의 일단에 제2전원전압이 인가됨과 더불어 다른 단에는 출력단자가 접속되고, 제4 및 제5트랜지스터의 일단이 출력단자에 각각 접속됨과 더불어 다른 단에 제1전원전압이 각각 인가되며, 제4트랜지스터의 게이트가 입력단자에 접속되면서, 제5트랜지스터의 게이트에 제어신호의 상보적인 신호가 인가되도록 구성되는 것을 특징으로 하는 BiMOS 논리회로.
  2. 제1항에 있어서, 상기 제3트랜지스터는 NPN형인 것을 특징으로 하는 BiMOS 논리회로.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019880003258A 1987-03-27 1988-03-25 BiMOS 논리회로 KR900008799B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP62-73462 1987-03-27
JP62073462A JPH07120727B2 (ja) 1987-03-27 1987-03-27 ＢｉＭＯＳ論理回路

Publications (2)

Publication Number Publication Date
KR880012009A true KR880012009A (ko) 1988-10-31
KR900008799B1 KR900008799B1 (ko) 1990-11-29

Family

ID=13518948

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019880003258A KR900008799B1 (ko) 1987-03-27 1988-03-25 BiMOS 논리회로

Country Status (3)

Country Link
US (1) US4804868A (ko)
JP (1) JPH07120727B2 (ko)
KR (1) KR900008799B1 (ko)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4926069A (en) * 1987-08-17 1990-05-15 Nec Corporation Bi-MOS circuit capable of high speed operation with low power consumption
US5065048A (en) * 1988-09-19 1991-11-12 Hitachi, Ltd. Semiconductor logic circuit with noise suppression circuit
US5006730A (en) * 1989-05-01 1991-04-09 Motorola, Inc. BIMOS logic gates
US4952823A (en) * 1989-05-03 1990-08-28 Advanced Micro Devices, Inc. Bicmos decoder
JPH02305220A (ja) * 1989-05-19 1990-12-18 Fujitsu Ltd Ｂｉ―ｃｍｏｓ回路
JPH03158018A (ja) * 1989-11-15 1991-07-08 Nec Corp 入力回路
US5216298A (en) * 1989-12-14 1993-06-01 Mitsubishi Denki Kabushiki Kaisha ECL input buffer for BiCMOS
US5289021A (en) * 1990-05-15 1994-02-22 Siarc Basic cell architecture for mask programmable gate array with 3 or more size transistors
US5055716A (en) * 1990-05-15 1991-10-08 Siarc Basic cell for bicmos gate array
US5068548A (en) * 1990-05-15 1991-11-26 Siarc Bicmos logic circuit for basic applications
US5107142A (en) * 1990-10-29 1992-04-21 Sun Microsystems, Inc. Apparatus for minimizing the reverse bias breakdown of emitter base junction of an output transistor in a tristate bicmos driver circuit
US5432462A (en) * 1993-04-30 1995-07-11 Motorola, Inc. Input buffer circuit having sleep mode and bus hold function
JP3162561B2 (ja) * 1993-12-24 2001-05-08 株式会社東芝 Ｃｍｏｓ論理回路
US5612638A (en) * 1994-08-17 1997-03-18 Microunity Systems Engineering, Inc. Time multiplexed ratioed logic
US5723883A (en) * 1995-11-14 1998-03-03 In-Chip Gate array cell architecture and routing scheme
US6617892B2 (en) * 1998-09-18 2003-09-09 Intel Corporation Single ended interconnect systems

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57141128A (en) * 1981-02-25 1982-09-01 Toshiba Corp Complementary mos logical circuit
JPS57157639A (en) * 1981-03-24 1982-09-29 Toshiba Corp Semiconductor circuit
JPH07107973B2 (ja) * 1984-03-26 1995-11-15 株式会社日立製作所 スイツチング回路
JPS62254460A (ja) * 1986-04-26 1987-11-06 Toshiba Corp Ｂｉ−ＣＭＯＳ論理回路

Also Published As

Publication number Publication date
JPH07120727B2 (ja) 1995-12-20
KR900008799B1 (ko) 1990-11-29
US4804868A (en) 1989-02-14
JPS63240126A (ja) 1988-10-05

Similar Documents

Publication Publication Date Title
KR880010575A (ko) 논리회로
KR880012009A (ko) BiMOS 논리회로
KR850006783A (ko) 스위칭 회로
KR880012014A (ko) Bimos 논리회로
KR880001108A (ko) Cmos 입력회로
KR860000719A (ko) 상보형(相補型)Bi-MIS 게이트회로
KR870006728A (ko) Bimos 회로
KR870009543A (ko) 차동 증폭 회로
KR880010576A (ko) 논리회로
KR880001111A (ko) 반도체 집적회로
KR950007285A (ko) 플립플롭형 증폭 회로
KR900002558A (ko) 출력회로
KR860009424A (ko) 반도체 집적 회로
KR890001274A (ko) 전류미러회로
KR860003712A (ko) 논리게이트 회로
KR910016077A (ko) 반도체집적회로
KR880011996A (ko) 차동증폭기
KR910021008A (ko) 전류전달회로
KR920015734A (ko) 입력 버퍼 재생 래치
KR910008978A (ko) 출력회로
KR850007179A (ko) 집적 논리회로
KR850008253A (ko) 차동 증폭기
KR900004096A (ko) 증폭회로
KR910010866A (ko) Bi-CMOS회로
KR890011195A (ko) 증폭회로

Legal Events

Date Code Title Description
A201 Request for examination
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20031030

Year of fee payment: 14

LAPS Lapse due to unpaid annual fee