KR880001060A - 반도체 장치 제조공정 - Google Patents

반도체 장치 제조공정 Download PDF

Info

Publication number
KR880001060A
KR880001060A KR870004798A KR870004798A KR880001060A KR 880001060 A KR880001060 A KR 880001060A KR 870004798 A KR870004798 A KR 870004798A KR 870004798 A KR870004798 A KR 870004798A KR 880001060 A KR880001060 A KR 880001060A
Authority
KR
South Korea
Prior art keywords
semiconductor device
device manufacturing
manufacturing process
indium phosphide
atoms
Prior art date
Application number
KR870004798A
Other languages
English (en)
Other versions
KR910008713B1 (ko
Inventor
덱스터 죤스턴 2세 윌버
앤롱 쥬디스
티멘 맥크랜더 앨버트
슈와츠 버트람
싱그 소바
Original Assignee
오레그 이, 앨버
아메리칸 텔리폰 앤드 텔레그라프 캄파니
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 오레그 이, 앨버, 아메리칸 텔리폰 앤드 텔레그라프 캄파니 filed Critical 오레그 이, 앨버
Publication of KR880001060A publication Critical patent/KR880001060A/ko
Application granted granted Critical
Publication of KR910008713B1 publication Critical patent/KR910008713B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/92—Capacitors having potential barriers
    • H01L29/94—Metal-insulator-semiconductors, e.g. MOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/2654—Bombardment with radiation with high-energy radiation producing ion implantation in AIIIBV compounds
    • H01L21/26546—Bombardment with radiation with high-energy radiation producing ion implantation in AIIIBV compounds of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H01L21/3245—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering of AIIIBV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Manufacturing & Machinery (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Ceramic Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Recrystallisation Techniques (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

내용 없음

Description

반도체 장치 제조공정
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 따라서 제조한 공핍형, n - 채널, 금속 - 절연체 - 반도체 전계효과 트랜지스터(MISFET)의 측면도. 제2도는 본 발명에 따라서 제조한 n - 채널과, 금속 - 반도체 전계효과 트랜지스터(MESFET)의 측면도. 제3도는 본 발명에 따라서 제조한 n채널, 증가형, 금속 - 절연체 - 반도체 전계효과 트랜지스터(MISFET)의 측면도.

Claims (12)

  1. n형 또는 p형 인듐 인화물로 이루어지는 기판 및 반-절연 인듐 인화물로 이루어지고 상기 기판의 적어도 일부의 표면과 접촉하는 제1영역을 포함하는 장치를 제조하기 위한 공정에 있어서, 반-절연 인듐 인화물의 층은 철로 도우프 되어 있으면서 MOCVD로 증식되어 있으며, 적어도 제1영역의 일부분은 풀림에 이어서 이온 주입에 의해 캐리어가 활성화되는 것을 특징으로 하는 반도체장치 제조공정.
  2. 제1항에 있어서, 철의 농도는 1015및 1018atoms/cm3사이의 농도인 것을 특징으로 하는 반도체장치 제조공정.
  3. 제1항에 있어서, 반절연 인듐 인화물층 표면의 결함도는 5×103defects/cm2보다 적으며 양호하게는 103defects/cm2또는 100defects/cm2또는 10defects/cm|2보다 적은 것을 특징으로 하는 반도체장치 제조공정.
  4. 제1항에 있어서, 주입되는 이온을 실리콘, 게르마늄, 주석, 유황, 셀레늄 및 텔륨으로부터 선택된 적어도 하나의 도우너 이온, 또는 아연, 카드뮴, 수은, 베릴륨, 마그네슘 및 망간으로부터 선택된 적어도 하나의 억셉터 이온인 것을 특징으로 하는 반도체장치 제조공정.
  5. 제1항에 있어서, 이온 주입의 이온 에너지는 100 및 800kev 사이이며 양호하게는 300 및 500kev 사이 또는 340 및 410kev 사이인 것을 특징으로 하는 반도체장치 제조공정.
  6. 제1항에 있어서, 상기 풀림 작용은 일분 및 한시간 사이, 양호하게는 15 및 20분 사이의 기간동안 600내지 850℃의 온도범위에서 실행되는 것을 특징으로 하는반도체장치 제조공정.
  7. 제1항에 있어서, 상기풀림 작용은 인화물과 가스로, 양호하게는 H2에 대해 PH3로 이루어지는 대기권에서 실행되는 것을 특징으로 하는 반도체장치 제조공정.
  8. 제1항에 있어서, 상기 이온주입은 100 및 300℃사이의 온도 범위에서 이루어지는 것을 특징으로 하는 반도체장치 제조공정.
  9. 제1항에 있어서, 제1영역의 두께는 1/2 및 10㎛, 양호하게는 1 및 4㎛ 또는 2 및 3㎛ 사이인 것을 특징으로 하는 반도체장치 제조공정.
  10. 제1항에 있어서, n-형 인듐 인화물은 1×1017atoms/cm3에서 포화까지, 양호하게는 약 8×1018에서 3.5×1019atoms/cm3까지의 농도 범위에서 유황으로 도우프 되는 것을 특징으로 하는 반도체장치 제조공정.
  11. 제1항에 있어서, p-형 인듐 인화물은 약 1×107에서 2×1018atoms/cm3까지의 농도 범위에서 아연으로 도우프 되는 것을 특징으로 하는 반도체장치 제조공정.
  12. 제1항에 있어서, 상기 장치는 적어도 하나의 공핍형 MISFET 또는 적어도 하나의 MESFET 또는 적어도 하나의 증가형 MISFET 또는 적어도 하나의 JFET, 또는 FET의 적합한 조합을 포함하는 적어도 하나의 전계효과 트랜지스터를 포함하는 것을 특징으로 하는 반도체장치 제조공정.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019870004798A 1986-05-16 1987-05-15 반도체 장치 제조공정 KR910008713B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US80-864,198 1986-05-16
US06/864,198 US4738934A (en) 1986-05-16 1986-05-16 Method of making indium phosphide devices
US864198 1986-05-16

Publications (2)

Publication Number Publication Date
KR880001060A true KR880001060A (ko) 1988-03-31
KR910008713B1 KR910008713B1 (ko) 1991-10-19

Family

ID=25342732

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019870004798A KR910008713B1 (ko) 1986-05-16 1987-05-15 반도체 장치 제조공정

Country Status (7)

Country Link
US (1) US4738934A (ko)
EP (1) EP0251458B1 (ko)
JP (1) JPH0716003B2 (ko)
KR (1) KR910008713B1 (ko)
CA (1) CA1332696C (ko)
DE (1) DE3784565T2 (ko)
HK (1) HK117393A (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100451661B1 (ko) * 1995-11-21 2004-11-20 몬테카티니 테크놀로지 에스. 알. 엘. 에틸렌을옥시클로리네이션하기위한촉매,이촉매의제조방법및이촉매를사용한옥시클로리네이션방법

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR880009419A (ko) * 1987-01-26 1988-09-15 이찌하라 시로 반도체소자의 제조방법 및 그 방법에 의해 제조된 반도체 소자
GB8913198D0 (en) * 1989-06-08 1989-07-26 British Telecomm Guard ring structure
CZ279488B6 (cs) * 1990-09-25 1995-05-17 Lonza A.G. Způsob mikrobiologické výroby hydroxylovaných heterocyklů
US5656538A (en) * 1995-03-24 1997-08-12 The Board Of Trustees Of The University Of Illinois Halide dopant process for producing semi-insulating group III-V regions for semiconductor devices
US5821147A (en) * 1995-12-11 1998-10-13 Lucent Technologies, Inc. Integrated circuit fabrication
US5861335A (en) * 1997-03-21 1999-01-19 Advanced Micro Devices, Inc. Semiconductor fabrication employing a post-implant anneal within a low temperature high pressure nitrogen ambient to improve channel and gate oxide reliability
US6214678B1 (en) * 1997-05-21 2001-04-10 Hughes Electronics Corp Growth technique for low noise high electron mobility transistors by metal organic vapor phase epitaxy
US6060402A (en) * 1998-07-23 2000-05-09 The Whitaker Corporation Process for selective recess etching of epitaxial field effect transistors with a novel etch-stop layer
JP2000100829A (ja) * 1998-09-25 2000-04-07 Sony Corp 接合型電界効果トランジスタおよびその製造方法
US6051865A (en) * 1998-11-09 2000-04-18 Advanced Micro Devices, Inc. Transistor having a barrier layer below a high permittivity gate dielectric
US6287946B1 (en) * 1999-05-05 2001-09-11 Hrl Laboratories, Llc Fabrication of low resistance, non-alloyed, ohmic contacts to InP using non-stoichiometric InP layers
US6891202B2 (en) * 2001-12-14 2005-05-10 Infinera Corporation Oxygen-doped Al-containing current blocking layers in active semiconductor devices
FR2845523B1 (fr) * 2002-10-07 2005-10-28 Procede pour realiser un substrat par transfert d'une plaquette donneuse comportant des especes etrangeres, et plaquette donneuse associee
US20090072205A1 (en) * 2003-05-07 2009-03-19 Sumitomo Electric Industries, Ltd. Indium phosphide substrate, indium phosphide single crystal and process for producing them
US20070138515A1 (en) * 2005-12-19 2007-06-21 M/A-Com, Inc. Dual field plate MESFET
US7485514B2 (en) * 2006-01-05 2009-02-03 Winslow Thomas A Method for fabricating a MESFET
US8759225B2 (en) * 2012-09-04 2014-06-24 Taiwan Semiconductor Manufacturing Co., Ltd. Method to form a CMOS image sensor
EP2982783A4 (en) * 2013-03-26 2017-01-04 JX Nippon Mining & Metals Corporation Compound semiconductor wafer, photoelectric conversion element, and method for producing group iii-v compound semiconductor single crystals
US8941123B2 (en) * 2013-05-30 2015-01-27 International Business Machines Corporation Local interconnects by metal-III-V alloy wiring in semi-insulating III-V substrates
RU2654984C1 (ru) * 2017-07-05 2018-05-23 Федеральное государственное бюджетное образовательное учреждение высшего образования "Чеченский государственный университет" Способ изготовления легированных областей

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4404172A (en) * 1981-01-05 1983-09-13 Western Electric Company, Inc. Method and apparatus for forming and growing a single crystal of a semiconductor compound
US4601095A (en) * 1981-10-27 1986-07-22 Sumitomo Electric Industries, Ltd. Process for fabricating a Schottky-barrier gate field effect transistor
FR2517120A1 (fr) * 1981-11-26 1983-05-27 Michel Salvi Procede de fabrication d'un composant semiconducteur par diffusion avec implantation ionique prealable et composant obtenu
JPS58145154A (ja) * 1982-02-22 1983-08-29 Nec Corp 電界効果形半導体装置
JPS5950567A (ja) * 1982-09-16 1984-03-23 Hitachi Ltd 電界効果トランジスタの製造方法
US4505023A (en) * 1982-09-29 1985-03-19 The United States Of America As Represented By The Secretary Of The Navy Method of making a planar INP insulated gate field transistor by a virtual self-aligned process
US4611388A (en) * 1983-04-14 1986-09-16 Allied Corporation Method of forming an indium phosphide-boron phosphide heterojunction bipolar transistor
US4544417A (en) * 1983-05-27 1985-10-01 Westinghouse Electric Corp. Transient capless annealing process for the activation of ion implanted compound semiconductors
US4555273A (en) * 1984-02-27 1985-11-26 The United States Of America As Represented By The Secretary Of The Navy Furnace transient anneal process
JPS6149484A (ja) * 1984-08-18 1986-03-11 Matsushita Electric Ind Co Ltd 化合物半導体素子及びその製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100451661B1 (ko) * 1995-11-21 2004-11-20 몬테카티니 테크놀로지 에스. 알. 엘. 에틸렌을옥시클로리네이션하기위한촉매,이촉매의제조방법및이촉매를사용한옥시클로리네이션방법

Also Published As

Publication number Publication date
KR910008713B1 (ko) 1991-10-19
CA1332696C (en) 1994-10-25
EP0251458A2 (en) 1988-01-07
HK117393A (en) 1993-11-05
JPH0716003B2 (ja) 1995-02-22
EP0251458B1 (en) 1993-03-10
DE3784565T2 (de) 1993-06-24
JPS62283671A (ja) 1987-12-09
EP0251458A3 (en) 1988-09-14
US4738934A (en) 1988-04-19
DE3784565D1 (de) 1993-04-15

Similar Documents

Publication Publication Date Title
KR880001060A (ko) 반도체 장치 제조공정
KR850002177A (ko) 얕은 n형 영역을 형성하는 방법
KR890003044A (ko) 반도체 장치 및 그의 제조방법
IE52184B1 (en) Device isolation in silicon semiconductor substrates
KR950034738A (ko) 박막 트랜지스터의 구조 및 제조방법
KR870006679A (ko) 전기효과 트랜지스터
EP0414400A3 (en) Mosfet depletion device
JPS5743455A (en) Complementary type semiconductor device
GB1503249A (en) Semiconductor devices
KR930005272A (ko) Ldd형 mos 트랜지스터 및 그의 제조방법
KR950026029A (ko) Mos트랜지스터 반도체 장치 및 그의 제조방법
Anholt et al. Mechanism of EL2 effects on GaAs field‐effect transistor threshold voltages
KR920003555A (ko) 등온이단계 급속 열처리에 의한 내열성 자기정렬 게이트 GaAs MESFET의 제조방법
KR940004711A (ko) 폴리실리콘층 형성방법
KR920015632A (ko) 소이모스소자 제조방법
KR940004851A (ko) 모스(mos) 트랜지스터 제조방법
KR910005441A (ko) 실리사이드를 사용한 매설 접촉 형성방법
KR950015569A (ko) 반도체장치의 제조방법
KR910010714A (ko) 메모리 집적회로 및 그 제조공정
KR960039216A (ko) Soi기판을 사용하는 반도체장치의 트랜지스터 제조방법
JPS6449266A (en) Transistor
KR890004399A (ko) 집적 반도체회로를 내포하고 있는 기판에 저고유 접촉저항을 갖는 접점을 제조하는 방법
EP0309828A3 (en) An electronic semiconductor device, in particular a silicon-gate field-effect mos transistor, for high input voltages
KR910020940A (ko) 고 접합파괴전압을 갖는 모오스 트랜지스터 및 그 제조방법
KR880013258A (ko) 반도체 장치의 제조방법

Legal Events

Date Code Title Description
A201 Request for examination
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20060929

Year of fee payment: 16

EXPY Expiration of term