KR870004525A - 게이트된 전송회로(Gated transmission circuit) - Google Patents

게이트된 전송회로(Gated transmission circuit) Download PDF

Info

Publication number
KR870004525A
KR870004525A KR1019860007612A KR860007612A KR870004525A KR 870004525 A KR870004525 A KR 870004525A KR 1019860007612 A KR1019860007612 A KR 1019860007612A KR 860007612 A KR860007612 A KR 860007612A KR 870004525 A KR870004525 A KR 870004525A
Authority
KR
South Korea
Prior art keywords
signal
transistor
transistors
conduction
field effect
Prior art date
Application number
KR1019860007612A
Other languages
English (en)
Other versions
KR950001951B1 (ko
Inventor
오스틴 켄네스
Original Assignee
디.제이.로베리지,리차드 에드워드 비바우.
필킹톤 마이크로-엘렉트로닉스 리미티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from GB858526143A external-priority patent/GB8526143D0/en
Priority claimed from GB868617705A external-priority patent/GB8617705D0/en
Application filed by 디.제이.로베리지,리차드 에드워드 비바우., 필킹톤 마이크로-엘렉트로닉스 리미티드 filed Critical 디.제이.로베리지,리차드 에드워드 비바우.
Publication of KR870004525A publication Critical patent/KR870004525A/ko
Application granted granted Critical
Publication of KR950001951B1 publication Critical patent/KR950001951B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/331—Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1735—Controllable logic circuits by wiring, e.g. uncommitted logic arrays
    • H03K19/1736—Controllable logic circuits by wiring, e.g. uncommitted logic arrays in which the wiring can be modified
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/02—Shaping pulses by amplifying
    • H03K5/026—Shaping pulses by amplifying with a bidirectional operation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Geometry (AREA)
  • Evolutionary Computation (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Logic Circuits (AREA)
  • Transmitters (AREA)
  • Reduction Or Emphasis Of Bandwidth Of Signals (AREA)
  • Vehicle Body Suspensions (AREA)
  • Dram (AREA)
  • Electronic Switches (AREA)

Abstract

내용 없음

Description

게이트된 전송회로(Gatedtransmissioncircuit)
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 따라 선택적 연결을 갖는 게이트 입력과 함께 논리 게이트 위치를 도시한 회로도.
제2A-2C도는 배치가능의 논리회로를 도시한 도면.
* 도면의 주요부분에 대한 부호설명
10:논리회로 12:게이트(Gate)입력
20:신호통과 트랜지스터 22:제어전극(control electrode)
24,26:드레인전극 30,50:선택회로
40:재충전회로(refresh circuit) 42:래치 레지스터(latch register)

Claims (10)

  1. 하나의 단일 신호통과 트랜지스터가 트랜지스터 전극중 하나(24A,B)로 연결되는 비트신호 입력(28A,B)과 다른 한 전극(26A,B)으로부터의 비트신호 출력(12A,B) 사이에 연결되어지는 하나의 단일 신호통과 트랜지스터(20A,B)와 전도 제어전극(2A,B)이 일시적이나 각각 규정된 간격으로 이어지는 에너지 주입(38A,B)을 위해 연결되어지는 스위칭회로(32,34)로 구성되는 적어도 하나의 게이트된 이진신호 전송회로를 포함하며, 신호통과 트랜지스터(20A,B) 고유의 방전되지 않은 정전용량 때문에 존속하는 전도에 따라 전술한 연속적인 에너지 주입 사이에서 신호를 통과시키도록 신호통과 트랜지스터가 동작되어짐을 특징으로 하는 전계효과 반도체 집적회로.
  2. 제1항에 있어서, 스위칭 회로(32,34)가 단일 신호통과 트랜지스터(20A,B), 전도 제어전극(22A,B)의 에너지 주입(38A,B)을 결정하는 신호전도가 가능해 지도록 하거나 그렇지 않으면 전도 제어전극(22A,B)을 플로오링 상태로 남기도록 연결된 제1전계효과 트랜지스터(32A,B)를 포함함을 특징으로하는 집적회로.
  3. 제2항에 있어서, 스위칭회로(32,34)가 두 전도 가능신호(36R,C)에 따라 제1전계효과 트랜지스터(32A,B)의 전도 가능을 제어하도록 제1전계효과 트랜지스터와 함께 연결되는 제2전계효과 트랜지스터(34A,B)를 포함함을 특징으로 하는 집적회로.
  4. 제3항에 있어서, 제2트랜지스터(34A,B)가 제1트랜지스터(32A,B)와 직렬로 연결되어 전술한 전도가 가능해지도록 하므로써 두 트랜지스터(32,34)가 동시에 전도 가능하게 되고 에너지 가입신호가 전술한 다른 트랜지스터를 통하여 적용되는 때에만 신호 통과 트랜지스터가 전도되도록 에너지를 주입 받도록 함을 특징으로 하는 집적회로.
  5. 제2-4항까지 항중 어느 한항에 있어서, 전술한 트랜지스터(32,34)가 신호등과 트랜지스터의 채널형태와 반대인 채널형태를 가짐을 특징으로 하는 집적회로.
  6. 제2-5항까지의 항중 어느 한항에 있어서, 전도 가능신호를 전술한 스위칭회로에 공급하기 위해 반복하여 적당한 간격으로 동작하는 재충전 제어회로(40)을 더욱 포함함을 특징으로 하는 집적회로.
  7. 제6항에 있어서, 에너지 주입 신호의 공급을 제어하는 래치 레지스터(42)를 더욱 포함함을 특징으로 하는 집적회로.
  8. 전술한 항중 어느 한항에 있어서, 하나의 논리회로(10)를 더욱 더 포함하며, 이같은 논리회로의 압출력(12A,B)이 선택적 연결통로를 포함하고, 연결통로 각각이 전술한 단일 신호통과 트랜지스터(20A,B)를 포함함을 특징으로 하는 집적회로.
  9. 전술한 항중 어느 한항에 있어서, 고유 게이트 정전용량 또는 각 신호통과 트랜지스터(20A,B)가 집적회로의 다른 트랜지스터(32,34)에 관계하여 증가됨을 특징으로하는 집적회로.
  10. 도면에 도시된 회로와 정확히 일치하는 적어도 하나의 신호 전송회로를 갖는 전계효과 반도체 집적회로.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019860007612A 1985-10-23 1986-09-10 게이트된 전송회로(Gated transmission circuit) KR950001951B1 (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
GB858526143A GB8526143D0 (en) 1985-10-23 1985-10-23 Semiconductor integrated circuits
GB8526143 1985-10-23
GB8617705 1986-07-19
GB868617705A GB8617705D0 (en) 1986-07-19 1986-07-19 Semiconductor integrated circuits/systems

Publications (2)

Publication Number Publication Date
KR870004525A true KR870004525A (ko) 1987-05-11
KR950001951B1 KR950001951B1 (ko) 1995-03-07

Family

ID=26289921

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019860007612A KR950001951B1 (ko) 1985-10-23 1986-09-10 게이트된 전송회로(Gated transmission circuit)

Country Status (7)

Country Link
US (1) US4868419A (ko)
EP (1) EP0220816B1 (ko)
JP (1) JPH07109710B2 (ko)
KR (1) KR950001951B1 (ko)
AT (1) ATE77184T1 (ko)
DE (1) DE3685629T2 (ko)
GB (1) GB2182220B (ko)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB8621357D0 (en) * 1986-09-04 1986-10-15 Mcallister R I Hinged barrier semiconductor integrated circuits
DE68925121T2 (de) * 1988-10-05 1996-06-13 Quickturn Systems Inc Verfahren zur verwendung einer elektronisch wiederkonfigurierbaren gatterfeld-logik und dadurch hergestelltes gerät
US5452231A (en) * 1988-10-05 1995-09-19 Quickturn Design Systems, Inc. Hierarchically connected reconfigurable logic assembly
US5329470A (en) * 1988-12-02 1994-07-12 Quickturn Systems, Inc. Reconfigurable hardware emulation system
US5109353A (en) 1988-12-02 1992-04-28 Quickturn Systems, Incorporated Apparatus for emulation of electronic hardware system
US5322812A (en) 1991-03-20 1994-06-21 Crosspoint Solutions, Inc. Improved method of fabricating antifuses in an integrated circuit device and resulting structure
JP3922653B2 (ja) * 1993-03-17 2007-05-30 ゲイトフィールド・コーポレイション ランダムアクセスメモリ（ｒａｍ）ベースのコンフィギュラブルアレイ
US5680583A (en) * 1994-02-16 1997-10-21 Arkos Design, Inc. Method and apparatus for a trace buffer in an emulation system
JPH08139579A (ja) * 1994-11-15 1996-05-31 Mitsubishi Electric Corp 電流源及び半導体集積回路装置
US5457418A (en) * 1994-12-05 1995-10-10 National Semiconductor Corporation Track and hold circuit with an input transistor held on during hold mode
US5541531A (en) * 1995-05-01 1996-07-30 Ford Motor Company Switch capacitor interface circuit
US5841967A (en) 1996-10-17 1998-11-24 Quickturn Design Systems, Inc. Method and apparatus for design verification using emulation and simulation
US5960191A (en) 1997-05-30 1999-09-28 Quickturn Design Systems, Inc. Emulation system with time-multiplexed interconnect
US5970240A (en) * 1997-06-25 1999-10-19 Quickturn Design Systems, Inc. Method and apparatus for configurable memory emulation
US7379859B2 (en) 2001-04-24 2008-05-27 Mentor Graphics Corporation Emulator with switching network connections
WO2016022552A1 (en) * 2014-08-04 2016-02-11 Emanuele Mandelli Scaling down pixel sizes in image sensors

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3675144A (en) * 1969-09-04 1972-07-04 Rca Corp Transmission gate and biasing circuits
US3718915A (en) * 1971-06-07 1973-02-27 Motorola Inc Opposite conductivity gating circuit for refreshing information in semiconductor memory cells
US3909674A (en) * 1974-03-28 1975-09-30 Rockwell International Corp Protection circuit for MOS driver
GB2048596B (en) * 1979-04-27 1983-11-02 Ch Polt I Device for switching dc circuits
JPS5686526A (en) * 1979-12-17 1981-07-14 Nec Corp Latch circuit
DE3018501A1 (de) * 1980-05-14 1981-11-19 Siemens AG, 1000 Berlin und 8000 München Schalter mit einem als source-folger betriebenen mis-pet
JPS5859626A (ja) * 1981-10-05 1983-04-08 Nec Corp トランスフア−ゲ−ト回路
JPS5883431A (ja) * 1981-11-13 1983-05-19 Toshiba Corp Ｍｏｓ型転送ゲ−ト回路
US4535401A (en) * 1982-06-30 1985-08-13 Texas Instruments Incorporated Apparatus and method for providing power from master controller to subcontrollers and data communication therebetween
US4652773A (en) * 1982-09-30 1987-03-24 Rca Corporation Integrated circuits with electrically erasable electrically programmable latch circuits therein for controlling operation
JPS6083294A (ja) * 1983-10-13 1985-05-11 Nec Corp 自動リフレツシユ回路
US4595845A (en) * 1984-03-13 1986-06-17 Mostek Corporation Non-overlapping clock CMOS circuit with two threshold voltages

Also Published As

Publication number Publication date
GB2182220A (en) 1987-05-07
DE3685629T2 (de) 1993-02-11
ATE77184T1 (de) 1992-06-15
EP0220816A3 (en) 1988-11-23
JPS62124692A (ja) 1987-06-05
US4868419A (en) 1989-09-19
GB2182220B (en) 1989-10-11
KR950001951B1 (ko) 1995-03-07
EP0220816A2 (en) 1987-05-06
JPH07109710B2 (ja) 1995-11-22
DE3685629D1 (de) 1992-07-16
GB8621819D0 (en) 1986-10-15
EP0220816B1 (en) 1992-06-10

Similar Documents

Publication Publication Date Title
US4612466A (en) High-speed output driver
KR870004525A (ko) 게이트된 전송회로(Gated transmission circuit)
US4216390A (en) Level shift circuit
US3675144A (en) Transmission gate and biasing circuits
US3651342A (en) Apparatus for increasing the speed of series connected transistors
GB1194754A (en) Semiconductor Bistable Circuit Arrangements
GB1127687A (en) Logic circuitry
JPH035692B2 (ko)
EP0110060A1 (en) FET voltage level shift circuitry
KR930017024A (ko) 판독 및 판독/기록 포트를 갖는 듀얼 포트 메모리
KR920004340B1 (ko) 전원절환회로
US4644185A (en) Self clocking CMOS latch
US3449594A (en) Logic circuits employing complementary pairs of field-effect transistors
US4386284A (en) Pulse generating circuit using current source
US4858167A (en) Parallel binary adder having grouped stages including dynamic logic to increase carry propagation speed
EP0062546B1 (en) Output circuit
GB1196216A (en) A Bistable Circuit
GB1172387A (en) Logical Circuit with Field Effect Transistors
KR900015465A (ko) Cmos 전압레벨 시프팅 및 함수회로
US3676705A (en) Logic circuits employing switches such as field-effect devices
KR950001992A (ko) 반도체 트랜지스터로 형성된 논리게이트 회로
SU932617A1 (ru) Устройство согласовани ТТЛ с МДП элементами
SU919089A1 (ru) Устройство согласовани ТТЛ-элементов с МДП-элементами
SU1182665A1 (ru) Элемент с трем состо ни ми
SU1081790A1 (ru) Дешифратор

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20060113

Year of fee payment: 12

EXPY Expiration of term