KR860009426A - 반도체 메모리 - Google Patents

반도체 메모리 Download PDF

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Publication number
KR860009426A
KR860009426A KR1019860004157A KR860004157A KR860009426A KR 860009426 A KR860009426 A KR 860009426A KR 1019860004157 A KR1019860004157 A KR 1019860004157A KR 860004157 A KR860004157 A KR 860004157A KR 860009426 A KR860009426 A KR 860009426A
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KR
South Korea
Prior art keywords
mos transistor
potential
signal input
connection point
control signal
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KR1019860004157A
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English (en)
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KR900008919B1 (ko
Inventor
히로시 사하라
하르끼 도다
시게오 오시마
Original Assignee
가부시끼가이샤 도오시바
와타리 수기이찌로
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Application filed by 가부시끼가이샤 도오시바, 와타리 수기이찌로 filed Critical 가부시끼가이샤 도오시바
Publication of KR860009426A publication Critical patent/KR860009426A/ko
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Publication of KR900008919B1 publication Critical patent/KR900008919B1/ko

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)

Abstract

내용 없음

Description

반도체 메모리
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제4도는 제1도에 접속되는 본 발명의 실시예에 대한 요부 회로도.
제5도는 본 발명에 따른 실시예의 동작을 나타내는 신호 파형도.
제6도는 본 발명의 다른 실시예에 따른 요부 회로도이다.
* 도면의 주요부분에 대한 부호의 설명
1, 2 : 장벽 트랜지스터 3, 4 : 감지용 플립플롭 트랜지스터
5 : 앞감지 구동용 트랜지스터 6 : 주감지 구동용 트랜지스터
21-23 : 트랜지스터 24 : 캐패시터
BL, BL : 비트선 øT: 게이트신호입력단
N1, N2: 접속점 ①,②,③ : 게이트단자
I/O, I/O : 입출력선 FF, FF : 플립플롭마디

Claims (3)

  1. 다이나믹형 메모리의 감지회로(3)(4)와 비트선(BL)(BL)사이에 MOS트랜지스터(1)(2)가 접속되고 있는 반도체 메모리에 있어서,
    상기 MOS 트랜지스터(1)(2)의 게이트 제어신호 입력단(øT)의 전위를 감지 동작시에는 비트선의 프리챠지전위(VDD)이하의 레벨까지 저하시켜 줌과 더불어 데이터 전송시에는 전원전압(VDD)에 MOS트랜지스터의 임계전압(VTH)을 더한값 이상의 레벨까지 상승시키는 수단을 구비한 것을 특징으로 하는 반도체 메모리.
  2. 제1항에 있어서, 상기 MOS트랜지스터(1)(2)의 게이트 제어신호 입력단(ΦT)과 전원단자(25)를 접속하는 제1MOS트랜지스터(21)와,
    상기 MOS트랜지스터(1)(2)의 게이트 제어신호 입력단(ΦT)과 캐패시터(24)를 매개하여 접속시키는 접속점(N2)기 상기 감지회로의 플립플롭을 구성하는 1쌍의 MOS트랜지스터를 공유하고 있는 마디(øSA)를 접속하는 제2MOS트랜지스터(22),
    상기 접속점(N2)과 전원단자(25)를 접속하는 제3MOS트랜지스터(23)를 구성시켜 줌으로써, 감지동작시에는 상기 접속점(N2)의 전위가 제2MOS트랜지스터(22)를 통하여 방전되는 한편, 데이터 전송시에는 제3MOS트랜지스터(23)를 통해 재충전함에 따라 감지동작시에는 상기 캐패시터(24)에서의 커플링에 의해 상기 게이트 제어신호 입력단(øT)의 전위가 비트선의 프리챠지전위 이하의 레벨까지 저하되고, 데이터 전송시에는 전원전압에 MOS트랜지스터(1)(2)의 임계전압(VTH)을 더한값 이상의 레벨까지 상승함을 특징으로 하는 반도체 메모리.
  3. 상기 제2항에 있어서, 상기 제2MOS트랜지스터(22)를 상기 접속점(N2)과 접지전위(VSS)사이에 접속하는 것을 특징으로 하는 반도체 메모리.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019860004157A 1985-05-28 1986-05-27 반도체 메모리 KR900008919B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP114807 1985-05-28
JP60114807A JPS61273792A (ja) 1985-05-28 1985-05-28 半導体メモリ

Publications (2)

Publication Number Publication Date
KR860009426A true KR860009426A (ko) 1986-12-22
KR900008919B1 KR900008919B1 (ko) 1990-12-11

Family

ID=14647180

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019860004157A KR900008919B1 (ko) 1985-05-28 1986-05-27 반도체 메모리

Country Status (5)

Country Link
US (1) US4794569A (ko)
EP (1) EP0204488B1 (ko)
JP (1) JPS61273792A (ko)
KR (1) KR900008919B1 (ko)
DE (1) DE3685993T2 (ko)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4931992B1 (en) * 1986-01-17 1998-03-03 Toshiba Kk Semiconductor memory having barrier transistors connected between sense and restore circuits
FR2667193B1 (fr) * 1990-09-25 1993-07-02 Sgs Thomson Microelectronics Circuit de precharge pour la lecture de memoires.
JPH0757466A (ja) * 1993-08-12 1995-03-03 Toshiba Corp 半導体集積回路

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53134337A (en) * 1977-03-25 1978-11-22 Hitachi Ltd Sense circuit
JPS5760589A (en) * 1980-09-30 1982-04-12 Nec Corp Memory circuit
JPH0711924B2 (ja) * 1981-07-22 1995-02-08 住友電気工業株式会社 長尺ソリツド海底電力ケ−ブル
DE3207498A1 (de) * 1982-03-02 1983-09-08 Siemens AG, 1000 Berlin und 8000 München Integrierter dynamischer schreib-lese-speicher
JPS6048073A (ja) * 1983-08-27 1985-03-15 富士ゼロックス株式会社 表示装置
US4598387A (en) * 1983-09-29 1986-07-01 Advanced Micro Devices, Inc. Capacitive memory signal doubler cell

Also Published As

Publication number Publication date
DE3685993D1 (de) 1992-08-20
JPS61273792A (ja) 1986-12-04
US4794569A (en) 1988-12-27
EP0204488B1 (en) 1992-07-15
KR900008919B1 (ko) 1990-12-11
EP0204488A3 (en) 1990-04-25
EP0204488A2 (en) 1986-12-10
DE3685993T2 (de) 1993-02-04

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