KR850002675A - 전계산화물에 배열된 채널정지부를 갖고있는 고밀도 mosfet 및 그 제조방법 - Google Patents

전계산화물에 배열된 채널정지부를 갖고있는 고밀도 mosfet 및 그 제조방법 Download PDF

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KR850002675A
KR850002675A KR1019840006053A KR840006053A KR850002675A KR 850002675 A KR850002675 A KR 850002675A KR 1019840006053 A KR1019840006053 A KR 1019840006053A KR 840006053 A KR840006053 A KR 840006053A KR 850002675 A KR850002675 A KR 850002675A
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oxide layer
active device
substrate
region
field oxide
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KR920009744B1 (ko
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와이. 첸 존 (외 1)
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알.엠.홀
휴우즈 에어크라프트 캄파니
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8236—Combination of enhancement and depletion transistors

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
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  • General Physics & Mathematics (AREA)
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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

내용 없음

Description

전계산화물에 배열된 채널정지부를 갖고있는 고밀도 MOSFET 및 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 따라 제조된 MOSFET의 횡단면도, 제2도, 제7도는 제1도의 장치의 절연구조물 부분을 제조하는 방법을 도시한 횡단면도.

Claims (10)

  1. 기질(12), 제1 도우퍼트를 포함하고 상기 기질(12)의 표면에 있는 활성장치영역(16), 제2 도우팬트를 포함하고 상기 활성장치영역에 인접한 상기 기질의 표면에 있는 채널정지부(26,27)및 상기 채널정지부(26,27)위에 놓여있고 인접하며, 한 연부가 상기 채널정지부(26,27)이 상기 활성장치영역(16)에 인접하는 지점에서 상기 채널정지부와 배열되는 전계산화물층(24)로 구성된 것을 특징으로 하는 MOSFET장치.
  2. 제1항에 있어서, 상기 전계 산화물층(24)의 두께 및 상기 채널정지부(26,27)내의 상기 제2 도우팬트의 농도가 상기 장치의 동작중에 상당한 양의 누설전류가 상기 전계 산화물(24) 밑에서 흐르지 못하게 하기에 충분한 것을 특징으로 하는 MOSFET장치.
  3. 한 연부가 상기 활성장치영역(15)의 경계점과 일렬로 배열되는 전계 산화물층(24)를 상기 활성장치영역(16)의 활성장치 표면영역(15)에 인접한 상기 기질(12)의 표면의 일부분상에 제공하는 수단, 상기 활성장치영역(15)위에 놓여있는 마스크(36)를 제공하는 수단 및 마스크(36)을 통과하기에는 불충분하지만, 상기 전계 산화물층(24)에 자체 배열되고 상기 활성장치영역(15)와 대응하게 배열된 채널정지부(40)을 형성하도록 상기 전계 산화물층(24)를 통과하기에는 충분한 에너지 레벨에서 이온들을 상기 기질내로 주입시키는 수단을 포함하는 것을 특징으로 하는 MOSFET장치 제조방법.
  4. 제3항에 있어서, 상기 이온들이 약 120KeV 내지 200KeV의 에너지레벨 및 약 5×1012이온/㎠ 내지 1×1013이온/㎠의 용량으로 주입되는 것을 특징으로 하는 방법.
  5. 제4항에 있어서, 상기 전계 산화물층의 두께가 약 4000Å 내지 6000Å정도인 것을 특징으로 하는 방법.
  6. 제4항에 있어서, 상기 전계 산화물층(24)를 형성하는 방법이, 상기 기질(12)의 표면상에 산화물층(24)를 형성하는 수단, 상기 활성장치영역(15)의 경계를 정하는 상기 산화물층(24)상에 임시마스크(34)를 형성하는 수단 및 상기 활성장치영역(15)를 노출시키기 위해 상기 임시마스크(34)에 의해 정해진 상기 산화물층(24)의 그 부분을 제거하는 수단을 포함하는 것을 특징으로 하는 방법.
  7. 제6항에 있어서, 상기 마스크(36)을 제공하는 방법이, 상기 기질의 표면위에 놓여있는 금속층(36)을 제공하는 수단 및 상기 금속층(36)위에 놓여있는 부분을 제거하기 위해, 상기 임시마스크(34)를 제거하는 수단을 포함하는 것을 특징으로 하는 방법.
  8. 제7항에 있어서, 상기 활성장치영역(15)를 노출시키는 수단 다음에 및 상기 마스크(36)를 제공하는 수단전에 상기 활성장치영역(16)이 상기 활성장치영역(15)밑에 제공되고, 도우팬트가 상기 기질(12)내로 주입되며, 상기 주입된 활성장치영역의 두께가 약 0.1㎛ 내지 0.3㎛정도인 것을 특징으로 하는 방법.
  9. 제8항에 있어서, 상기 도우팬트가 약 20keV 내지 30KeV의 에너지 레벨 및 7×1011이온/㎠내지 1.5×1012이온/㎠의 용량으로 주입되는 것을 특징으로 하는 방법.
  10. 제9항에 있어서, 상기 기질(12)가 실리콘으로 구성되고, 상기 전계 산화물층(24)가 이산화실리콘으로 구성되는 것을 특징으로 하는 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019840006053A 1983-09-30 1984-09-29 전계산화물에 배열된 채널 정지부를 갖고 있는 고밀도 mosfet 및 그 제조방법 KR920009744B1 (ko)

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US53792083A 1983-09-30 1983-09-30
US537,920 1983-09-30
US537920 1983-09-30

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KR920009744B1 KR920009744B1 (ko) 1992-10-22

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EP (1) EP0157780B1 (ko)
JP (1) JPH0616525B2 (ko)
KR (1) KR920009744B1 (ko)
DE (1) DE3376710D1 (ko)
IL (1) IL72336A (ko)
WO (1) WO1985001613A1 (ko)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5208168A (en) * 1990-11-26 1993-05-04 Motorola, Inc. Semiconductor device having punch-through protected buried contacts and method for making the same
KR100197656B1 (ko) * 1995-12-29 1999-07-01 김영환 반도체 에스.오.아이.소자의 제조방법

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5679446A (en) * 1979-12-04 1981-06-30 Chiyou Lsi Gijutsu Kenkyu Kumiai Production of semiconductor device
JPS56111241A (en) * 1980-02-01 1981-09-02 Chiyou Lsi Gijutsu Kenkyu Kumiai Preparation of semiconductor device
FR2506076A1 (fr) * 1981-05-12 1982-11-19 Efcis Procede de fabrication de circuits integres de type mos
JPS58121643A (ja) * 1982-01-13 1983-07-20 Toshiba Corp 半導体装置の製造方法
US4418094A (en) * 1982-03-02 1983-11-29 Texas Instruments Incorporated Vertical-etch direct moat isolation process
DE3371837D1 (en) * 1982-12-08 1987-07-02 Ibm Method for making semiconductor devices having a thick field dielectric and a self-aligned channel stopper
JPS59161069A (ja) * 1983-03-04 1984-09-11 Oki Electric Ind Co Ltd Ｍｏｓ型半導体装置の製造方法

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DE3376710D1 (en) 1988-06-23
IL72336A (en) 1988-04-29
EP0157780B1 (en) 1988-05-18
WO1985001613A1 (en) 1985-04-11
JPH0616525B2 (ja) 1994-03-02
KR920009744B1 (ko) 1992-10-22
EP0157780A1 (en) 1985-10-16
IL72336A0 (en) 1984-11-30
JPS61500046A (ja) 1986-01-09

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