KR20240136339A - 회로 기판의 제조방법 및 이에 사용하는 수지 시트 - Google Patents

회로 기판의 제조방법 및 이에 사용하는 수지 시트 Download PDF

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Publication number
KR20240136339A
KR20240136339A KR1020247023246A KR20247023246A KR20240136339A KR 20240136339 A KR20240136339 A KR 20240136339A KR 1020247023246 A KR1020247023246 A KR 1020247023246A KR 20247023246 A KR20247023246 A KR 20247023246A KR 20240136339 A KR20240136339 A KR 20240136339A
Authority
KR
South Korea
Prior art keywords
resin
substrate
resin composition
layer
composition layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
KR1020247023246A
Other languages
English (en)
Korean (ko)
Inventor
슈 이케히라
Original Assignee
아지노모토 가부시키가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 아지노모토 가부시키가이샤 filed Critical 아지노모토 가부시키가이샤
Publication of KR20240136339A publication Critical patent/KR20240136339A/ko
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09J—ADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J11/00—Features of adhesives not provided for in group C09J9/00, e.g. additives
    • C09J11/02—Non-macromolecular additives
    • C09J11/04—Non-macromolecular additives inorganic
    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09J—ADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J7/00—Adhesives in the form of films or foils
    • C09J7/30—Adhesives in the form of films or foils characterised by the adhesive composition
    • C09J7/38—Pressure-sensitive adhesives [PSA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/145—Organic substrates, e.g. plastic
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0055—After-treatment, e.g. cleaning or desmearing of holes
    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09J—ADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J2203/00—Applications of adhesives in processes or use of adhesives in the form of films or foils
    • C09J2203/326—Applications of adhesives in processes or use of adhesives in the form of films or foils for bonding electronic components such as wafers, chips or semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0203—Fillers and particles
    • H05K2201/0206—Materials
    • H05K2201/0212—Resin particles
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/049—Wire bonding

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Organic Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Inorganic Chemistry (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Laminated Bodies (AREA)
KR1020247023246A 2022-01-13 2023-01-11 회로 기판의 제조방법 및 이에 사용하는 수지 시트 Pending KR20240136339A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2022003660 2022-01-13
JPJP-P-2022-003660 2022-01-13
PCT/JP2023/000390 WO2023136253A1 (ja) 2022-01-13 2023-01-11 回路基板の製造方法及びそれに用いる樹脂シート

Publications (1)

Publication Number Publication Date
KR20240136339A true KR20240136339A (ko) 2024-09-13

Family

ID=87279096

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020247023246A Pending KR20240136339A (ko) 2022-01-13 2023-01-11 회로 기판의 제조방법 및 이에 사용하는 수지 시트

Country Status (6)

Country Link
US (1) US20240371823A1 (enExample)
JP (1) JPWO2023136253A1 (enExample)
KR (1) KR20240136339A (enExample)
CN (1) CN118648099A (enExample)
TW (1) TW202343693A (enExample)
WO (1) WO2023136253A1 (enExample)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWM632394U (zh) * 2022-06-15 2022-09-21 晶化科技股份有限公司 扇出型電子封裝結構

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018087986A (ja) 2016-03-31 2018-06-07 旭化成株式会社 感光性樹脂組成物、硬化レリーフパターンの製造方法及び半導体装置

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004221418A (ja) * 2003-01-16 2004-08-05 Casio Comput Co Ltd 半導体装置およびその製造方法
JP2004221417A (ja) * 2003-01-16 2004-08-05 Casio Comput Co Ltd 半導体装置およびその製造方法
WO2009113216A1 (ja) * 2008-03-10 2009-09-17 古河電気工業株式会社 電子部品加工用粘着テープ
JP5892780B2 (ja) * 2011-12-19 2016-03-23 日東電工株式会社 半導体装置の製造方法
US9184083B2 (en) * 2013-07-29 2015-11-10 3M Innovative Properties Company Apparatus, hybrid laminated body, method and materials for temporary substrate support
JP2015065321A (ja) * 2013-09-25 2015-04-09 日東電工株式会社 半導体装置の製造方法
WO2016063916A1 (ja) * 2014-10-23 2016-04-28 リンテック株式会社 表面保護用シート
JP6885000B2 (ja) * 2016-07-19 2021-06-09 昭和電工マテリアルズ株式会社 半導体再配線層形成用樹脂フィルム、半導体再配線層形成用複合フィルム、それらを用いた半導体装置及び半導体装置の製造方法
JP7067140B2 (ja) * 2017-03-29 2022-05-16 味の素株式会社 樹脂組成物
TWI773745B (zh) * 2017-04-24 2022-08-11 日商味之素股份有限公司 樹脂組成物
WO2019021672A1 (ja) * 2017-07-26 2019-01-31 日本電気硝子株式会社 支持ガラス基板及びこれを用いた積層基板
JP6960459B2 (ja) * 2017-08-04 2021-11-05 リンテック株式会社 半導体装置の製造方法
JP2019033124A (ja) * 2017-08-04 2019-02-28 リンテック株式会社 半導体装置の製造方法、及び接着積層体
KR102581569B1 (ko) * 2017-10-10 2023-10-05 아지노모토 가부시키가이샤 경화체 및 이의 제조방법, 수지 시트 및 수지 조성물
JP6939687B2 (ja) * 2018-04-16 2021-09-22 味の素株式会社 樹脂組成物
JP7174637B2 (ja) * 2019-01-28 2022-11-17 株式会社ダイセル 硬化性フイルム
JP7249907B2 (ja) * 2019-08-08 2023-03-31 新光電気工業株式会社 配線基板の製造方法及び積層構造
US11682626B2 (en) * 2020-01-29 2023-06-20 Taiwan Semiconductor Manufacturing Co., Ltd. Chamfered die of semiconductor package and method for forming the same
JP7287348B2 (ja) * 2020-05-28 2023-06-06 味の素株式会社 樹脂組成物
JP7470411B2 (ja) * 2020-09-30 2024-04-18 フジコピアン株式会社 ウェーハ加工用積層体、それを用いた薄型ウェーハの製造方法及び薄型ウェーハ個片化の製造方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018087986A (ja) 2016-03-31 2018-06-07 旭化成株式会社 感光性樹脂組成物、硬化レリーフパターンの製造方法及び半導体装置

Also Published As

Publication number Publication date
CN118648099A (zh) 2024-09-13
US20240371823A1 (en) 2024-11-07
JPWO2023136253A1 (enExample) 2023-07-20
TW202343693A (zh) 2023-11-01
WO2023136253A1 (ja) 2023-07-20

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R18-X000 Changes to party contact information recorded

St.27 status event code: A-3-3-R10-R18-oth-X000

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St.27 status event code: A-2-2-P10-P11-nap-X000