KR20130140759A - 흐름 없는 언더필 - Google Patents

흐름 없는 언더필 Download PDF

Info

Publication number
KR20130140759A
KR20130140759A KR1020137014121A KR20137014121A KR20130140759A KR 20130140759 A KR20130140759 A KR 20130140759A KR 1020137014121 A KR1020137014121 A KR 1020137014121A KR 20137014121 A KR20137014121 A KR 20137014121A KR 20130140759 A KR20130140759 A KR 20130140759A
Authority
KR
South Korea
Prior art keywords
conductive
post
component
microelectronic
conductive element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
KR1020137014121A
Other languages
English (en)
Korean (ko)
Inventor
벨가셈 하바
일야스 모하메드
엘리스 차우
상 2세 이
키쇼어 디사이
Original Assignee
테세라, 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 테세라, 인코포레이티드 filed Critical 테세라, 인코포레이티드
Publication of KR20130140759A publication Critical patent/KR20130140759A/ko
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/012—Manufacture or treatment of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07221—Aligning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H10W72/07236—Soldering or alloying
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H10W72/07252—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting changes in structures or sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H10W72/07253—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting changes in shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/221—Structures or relative sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/221—Structures or relative sizes
    • H10W72/227—Multiple bumps having different sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/231—Shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/953—Materials of bond pads not comprising solid metals or solid metalloids, e.g. polymers, ceramics or liquids
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)
KR1020137014121A 2010-11-02 2011-10-27 흐름 없는 언더필 Abandoned KR20130140759A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/938,068 US8697492B2 (en) 2010-11-02 2010-11-02 No flow underfill
US12/938,068 2010-11-02
PCT/US2011/058080 WO2012061199A2 (en) 2010-11-02 2011-10-27 No flow underfill

Related Child Applications (1)

Application Number Title Priority Date Filing Date
KR1020187015041A Division KR101967322B1 (ko) 2010-11-02 2011-10-27 흐름 없는 언더필

Publications (1)

Publication Number Publication Date
KR20130140759A true KR20130140759A (ko) 2013-12-24

Family

ID=44999895

Family Applications (2)

Application Number Title Priority Date Filing Date
KR1020137014121A Abandoned KR20130140759A (ko) 2010-11-02 2011-10-27 흐름 없는 언더필
KR1020187015041A Expired - Fee Related KR101967322B1 (ko) 2010-11-02 2011-10-27 흐름 없는 언더필

Family Applications After (1)

Application Number Title Priority Date Filing Date
KR1020187015041A Expired - Fee Related KR101967322B1 (ko) 2010-11-02 2011-10-27 흐름 없는 언더필

Country Status (6)

Country Link
US (2) US8697492B2 (https=)
JP (1) JP5649739B2 (https=)
KR (2) KR20130140759A (https=)
CN (1) CN103283007B (https=)
TW (1) TWI564972B (https=)
WO (1) WO2012061199A2 (https=)

Families Citing this family (51)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5592055B2 (ja) 2004-11-03 2014-09-17 テッセラ，インコーポレイテッド 積層パッケージングの改良
US8058101B2 (en) 2005-12-23 2011-11-15 Tessera, Inc. Microelectronic packages and methods therefor
US9159708B2 (en) 2010-07-19 2015-10-13 Tessera, Inc. Stackable molded microelectronic packages with area array unit connectors
US8482111B2 (en) 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
US20120146206A1 (en) * 2010-12-13 2012-06-14 Tessera Research Llc Pin attachment
US11830845B2 (en) 2011-05-03 2023-11-28 Tessera Llc Package-on-package assembly with wire bonds to encapsulation surface
KR101128063B1 (ko) 2011-05-03 2012-04-23 테세라, 인코포레이티드 캡슐화 층의 표면에 와이어 본드를 구비하는 패키지 적층형 어셈블리
US8618659B2 (en) 2011-05-03 2013-12-31 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US8963340B2 (en) * 2011-09-13 2015-02-24 International Business Machines Corporation No flow underfill or wafer level underfill and solder columns
US8836136B2 (en) 2011-10-17 2014-09-16 Invensas Corporation Package-on-package assembly with wire bond vias
US8586408B2 (en) * 2011-11-08 2013-11-19 Taiwan Semiconductor Manufacturing Company, Ltd. Contact and method of formation
US8946757B2 (en) 2012-02-17 2015-02-03 Invensas Corporation Heat spreading substrate with embedded interconnects
US8372741B1 (en) 2012-02-24 2013-02-12 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US9917035B2 (en) * 2012-10-24 2018-03-13 Taiwan Semiconductor Manufacturing Co., Ltd. Bump-on-trace interconnection structure for flip-chip packages
US9646923B2 (en) 2012-04-17 2017-05-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices
US8835228B2 (en) 2012-05-22 2014-09-16 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US9391008B2 (en) 2012-07-31 2016-07-12 Invensas Corporation Reconstituted wafer-level package DRAM
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
US8889486B2 (en) * 2012-09-05 2014-11-18 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for package on package structures
US9385098B2 (en) * 2012-11-21 2016-07-05 Nvidia Corporation Variable-size solder bump structures for integrated circuit packaging
US8878353B2 (en) 2012-12-20 2014-11-04 Invensas Corporation Structure for microelectronic packaging with bond elements to encapsulation surface
US9136254B2 (en) 2013-02-01 2015-09-15 Invensas Corporation Microelectronic package having wire bond vias and stiffening layer
US20140356986A1 (en) * 2013-05-31 2014-12-04 International Business Machines Corporation Precision controlled collapse chip connection mapping
US9167710B2 (en) 2013-08-07 2015-10-20 Invensas Corporation Embedded packaging with preformed vias
US9685365B2 (en) 2013-08-08 2017-06-20 Invensas Corporation Method of forming a wire bond having a free end
US20150076714A1 (en) 2013-09-16 2015-03-19 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
US9263394B2 (en) 2013-11-22 2016-02-16 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9583456B2 (en) 2013-11-22 2017-02-28 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9379074B2 (en) 2013-11-22 2016-06-28 Invensas Corporation Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
US9583411B2 (en) 2014-01-17 2017-02-28 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
US10381326B2 (en) 2014-05-28 2019-08-13 Invensas Corporation Structure and method for integrated circuits packaging with increased density
US9646917B2 (en) 2014-05-29 2017-05-09 Invensas Corporation Low CTE component with wire bond interconnects
US9412714B2 (en) 2014-05-30 2016-08-09 Invensas Corporation Wire bond support structure and microelectronic package including wire bonds therefrom
JP5873152B1 (ja) * 2014-09-29 2016-03-01 日本特殊陶業株式会社 配線基板
US9735084B2 (en) 2014-12-11 2017-08-15 Invensas Corporation Bond via array for thermal conductivity
US9888579B2 (en) 2015-03-05 2018-02-06 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
US9502372B1 (en) 2015-04-30 2016-11-22 Invensas Corporation Wafer-level packaging using wire bond wires in place of a redistribution layer
US9761554B2 (en) 2015-05-07 2017-09-12 Invensas Corporation Ball bonding metal wire bond wires to metal pads
US9603283B1 (en) * 2015-10-09 2017-03-21 Raytheon Company Electronic module with free-formed self-supported vertical interconnects
US10490528B2 (en) 2015-10-12 2019-11-26 Invensas Corporation Embedded wire bond wires
US9490222B1 (en) 2015-10-12 2016-11-08 Invensas Corporation Wire bond wires for interference shielding
US10332854B2 (en) 2015-10-23 2019-06-25 Invensas Corporation Anchoring structure of fine pitch bva
US10181457B2 (en) 2015-10-26 2019-01-15 Invensas Corporation Microelectronic package for wafer-level chip scale packaging with fan-out
US10043779B2 (en) 2015-11-17 2018-08-07 Invensas Corporation Packaged microelectronic device for a package-on-package device
US9659848B1 (en) 2015-11-18 2017-05-23 Invensas Corporation Stiffened wires for offset BVA
US9984992B2 (en) 2015-12-30 2018-05-29 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
KR101799668B1 (ko) * 2016-04-07 2017-11-20 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그 제조 방법
US9935075B2 (en) 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
US10299368B2 (en) 2016-12-21 2019-05-21 Invensas Corporation Surface integrated waveguides and circuit structures therefor
US10750614B2 (en) * 2017-06-12 2020-08-18 Invensas Corporation Deformable electrical contacts with conformable target pads
KR102830541B1 (ko) 2020-09-23 2025-07-07 삼성전자주식회사 반도체 칩의 접속 구조물 및 접속 구조물을 포함하는 반도체 패키지

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7022A (en) * 1850-01-15 Cideb-mill
JP2716336B2 (ja) * 1993-03-10 1998-02-18 日本電気株式会社 集積回路装置
US6177636B1 (en) 1994-12-29 2001-01-23 Tessera, Inc. Connection components with posts
JPH0997791A (ja) 1995-09-27 1997-04-08 Internatl Business Mach Corp <Ibm> バンプ構造、バンプの形成方法、実装接続体
JP3971500B2 (ja) 1998-02-20 2007-09-05 ソニー株式会社 半導体素子実装用配線基板の製造方法
US6225206B1 (en) 1999-05-10 2001-05-01 International Business Machines Corporation Flip chip C4 extension structure and process
AU2002245103A1 (en) * 2000-11-14 2002-07-30 Henkel Loctite Corporation Wafer applied fluxing and underfill material, and layered electronic assemblies manufactured therewith
US6599775B2 (en) 2001-05-18 2003-07-29 Advanpack Solutions Pte Ltd Method for forming a flip chip semiconductor package, a semiconductor package formed thereby, and a substrate therefor
US7323360B2 (en) 2001-10-26 2008-01-29 Intel Corporation Electronic assemblies with filled no-flow underfill
US8641913B2 (en) 2003-10-06 2014-02-04 Tessera, Inc. Fine pitch microcontacts and method for forming thereof
JP2006100552A (ja) 2004-09-29 2006-04-13 Rohm Co Ltd 配線基板および半導体装置
US7573137B2 (en) * 2006-03-31 2009-08-11 Texas Instruments Incorporated Controlling flip-chip techniques for concurrent ball bonds in semiconductor devices
JP2009158593A (ja) * 2007-12-25 2009-07-16 Tessera Interconnect Materials Inc バンプ構造およびその製造方法
JP5064288B2 (ja) * 2008-04-15 2012-10-31 新光電気工業株式会社 半導体装置の製造方法
JP4641551B2 (ja) * 2008-06-13 2011-03-02 富士通株式会社 半導体装置の製造方法
US20100044860A1 (en) 2008-08-21 2010-02-25 Tessera Interconnect Materials, Inc. Microelectronic substrate or element having conductive pads and metal posts joined thereto using bond layer
JP5056718B2 (ja) * 2008-10-16 2012-10-24 株式会社デンソー 電子装置の製造方法
US7569935B1 (en) * 2008-11-12 2009-08-04 Powertech Technology Inc. Pillar-to-pillar flip-chip assembly
US8008122B1 (en) * 2010-09-21 2011-08-30 International Business Machines Corporation Pressurized underfill cure

Also Published As

Publication number Publication date
US8697492B2 (en) 2014-04-15
KR20180061419A (ko) 2018-06-07
TWI564972B (zh) 2017-01-01
CN103283007B (zh) 2016-02-03
TW201225188A (en) 2012-06-16
WO2012061199A2 (en) 2012-05-10
JP2013541858A (ja) 2013-11-14
US20120104595A1 (en) 2012-05-03
CN103283007A (zh) 2013-09-04
JP5649739B2 (ja) 2015-01-07
US20140217584A1 (en) 2014-08-07
KR101967322B1 (ko) 2019-04-09
WO2012061199A3 (en) 2012-06-28
US9196581B2 (en) 2015-11-24

Similar Documents

Publication Publication Date Title
KR101967322B1 (ko) 흐름 없는 언더필
US11710718B2 (en) Structures and methods for low temperature bonding using nanoparticles
TWI545722B (zh) 具有堆疊面下連接晶粒之多晶片模組
US7749806B2 (en) Fabricating process of a chip package structure
US7640655B2 (en) Electronic component embedded board and its manufacturing method
US6537854B1 (en) Method for bonding IC chips having multi-layered bumps with corrugated surfaces and devices formed
TWI763841B (zh) 形成具有豎立指向的電子構件的電子裝置結構的方法及相關結構
US20160254247A1 (en) Fan-out WLP with package
US11973056B2 (en) Methods for low temperature bonding using nanoparticles
KR20100050457A (ko) 핀 인터페이스를 갖는 다층의 배선 요소
JP2014512695A (ja) 成形された低ｃｔｅ誘電体を有するインターポーザ
US6528889B1 (en) Electronic circuit device having adhesion-reinforcing pattern on a circuit board for flip-chip mounting an IC chip
KR101357765B1 (ko) 유연성을 갖는 마이크로 전자회로 조립체
US7960214B2 (en) Chip package
KR102050011B1 (ko) 반도체 패키지용 상호 연결 구조체 및 상호 연결 구조체의 제조 방법
JPH11163054A (ja) 半導体装置の構造及びその製造方法
US20070063344A1 (en) Chip package structure and bumping process
TWI393197B (zh) 晶片封裝
CN108305864A (zh) 新型端子
TWI393192B (zh) 晶片封裝結構製程
JPH11265959A (ja) パッケージ型半導体装置
TW201828396A (zh) 新型端子

Legal Events

Date Code Title Description
PA0105 International application

St.27 status event code: A-0-1-A10-A15-nap-PA0105

E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

A201 Request for examination
PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

A107 Divisional application of patent
PA0104 Divisional application for international application

St.27 status event code: A-0-1-A10-A18-div-PA0104

St.27 status event code: A-0-1-A10-A16-div-PA0104

NORF Unpaid initial registration fee
PC1904 Unpaid initial registration fee

St.27 status event code: A-2-2-U10-U14-oth-PC1904

St.27 status event code: N-2-6-B10-B12-nap-PC1904

P22-X000 Classification modified

St.27 status event code: A-2-2-P10-P22-nap-X000

PN2301 Change of applicant

St.27 status event code: A-3-3-R10-R13-asn-PN2301

St.27 status event code: A-3-3-R10-R11-asn-PN2301

R11 Change to the name of applicant or owner or transfer of ownership requested

Free format text: ST27 STATUS EVENT CODE: A-3-3-R10-R11-ASN-PN2301 (AS PROVIDED BY THE NATIONAL OFFICE)

R13 Change to the name of applicant or owner recorded

Free format text: ST27 STATUS EVENT CODE: A-3-3-R10-R13-ASN-PN2301 (AS PROVIDED BY THE NATIONAL OFFICE)