KR20110101876A - 매립 비트 라인을 갖는 반도체 장치 및 반도체 장치의 제조 방법 - Google Patents

매립 비트 라인을 갖는 반도체 장치 및 반도체 장치의 제조 방법 Download PDF

Info

Publication number
KR20110101876A
KR20110101876A KR1020100021211A KR20100021211A KR20110101876A KR 20110101876 A KR20110101876 A KR 20110101876A KR 1020100021211 A KR1020100021211 A KR 1020100021211A KR 20100021211 A KR20100021211 A KR 20100021211A KR 20110101876 A KR20110101876 A KR 20110101876A
Authority
KR
South Korea
Prior art keywords
semiconductor device
substrate
bit line
disposed
buried bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
KR1020100021211A
Other languages
English (en)
Korean (ko)
Inventor
윤재만
김희중
정현우
김현기
김강욱
오용철
Original Assignee
삼성전자주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 삼성전자주식회사 filed Critical 삼성전자주식회사
Priority to KR1020100021211A priority Critical patent/KR20110101876A/ko
Priority to US12/760,140 priority patent/US8373214B2/en
Priority to JP2010264982A priority patent/JP5722600B2/ja
Publication of KR20110101876A publication Critical patent/KR20110101876A/ko
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/318—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor the storage electrode having multiple segments
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Thin Film Transistor (AREA)
KR1020100021211A 2010-03-10 2010-03-10 매립 비트 라인을 갖는 반도체 장치 및 반도체 장치의 제조 방법 Ceased KR20110101876A (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1020100021211A KR20110101876A (ko) 2010-03-10 2010-03-10 매립 비트 라인을 갖는 반도체 장치 및 반도체 장치의 제조 방법
US12/760,140 US8373214B2 (en) 2010-03-10 2010-04-14 Semiconductor devices with buried bit lines and methods of manufacturing semiconductor devices
JP2010264982A JP5722600B2 (ja) 2010-03-10 2010-11-29 埋立ビットラインを有する半導体装置及び半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020100021211A KR20110101876A (ko) 2010-03-10 2010-03-10 매립 비트 라인을 갖는 반도체 장치 및 반도체 장치의 제조 방법

Publications (1)

Publication Number Publication Date
KR20110101876A true KR20110101876A (ko) 2011-09-16

Family

ID=44559130

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020100021211A Ceased KR20110101876A (ko) 2010-03-10 2010-03-10 매립 비트 라인을 갖는 반도체 장치 및 반도체 장치의 제조 방법

Country Status (3)

Country Link
US (1) US8373214B2 (enExample)
JP (1) JP5722600B2 (enExample)
KR (1) KR20110101876A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8836001B2 (en) 2012-03-19 2014-09-16 SK Hynix Inc. Semiconductor device having buried bit line, and method for fabricating the same

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110254085A1 (en) * 2010-04-16 2011-10-20 Hynix Semiconductor Inc. Semiconductor integrated circuit device having reduced unit cell area and method for manufacturing the same
KR101669261B1 (ko) * 2010-06-14 2016-10-25 삼성전자주식회사 수직 채널 트랜지스터를 구비한 반도체 소자 및 그 제조 방법
US8759178B2 (en) 2011-11-09 2014-06-24 Unisantis Electronics Singapore Pte. Ltd. Method for manufacturing semiconductor device and semiconductor device
US10438836B2 (en) 2011-11-09 2019-10-08 Unisantis Electronics Singapore Pte. Ltd. Method for manufacturing a semiconductor device
WO2013069102A1 (ja) * 2011-11-09 2013-05-16 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド 半導体装置の製造方法及び半導体装置
US9117690B2 (en) 2011-12-02 2015-08-25 Unisantis Electronics Singapore Pte. Ltd. Method for producing semiconductor device and semiconductor device
US8735971B2 (en) 2011-12-02 2014-05-27 Unisantis Electronics Singapore Pte. Ltd. Method for producing semiconductor device and semiconductor device
US9312257B2 (en) * 2012-02-29 2016-04-12 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US9023723B2 (en) * 2012-05-31 2015-05-05 Applied Materials, Inc. Method of fabricating a gate-all-around word line for a vertical channel DRAM
JP2014022390A (ja) * 2012-07-12 2014-02-03 Ps4 Luxco S A R L 半導体装置、ピラートランジスタのレイアウト方法及びそのレイアウト方法を用いて製造した半導体装置
KR101924020B1 (ko) 2012-10-18 2018-12-03 삼성전자주식회사 반도체 장치 및 이의 제조 방법
KR102001417B1 (ko) 2012-10-23 2019-07-19 삼성전자주식회사 반도체 장치
KR20140109741A (ko) * 2013-03-06 2014-09-16 에스케이하이닉스 주식회사 수직형 반도체 장치 및 제조 방법과 그 동작 방법
KR102029794B1 (ko) * 2013-03-15 2019-10-08 삼성전자주식회사 반도체 장치
JP5974066B2 (ja) * 2014-12-12 2016-08-23 ユニサンティス エレクトロニクス シンガポール プライベート リミテッドＵｎｉｓａｎｔｉｓ Ｅｌｅｃｔｒｏｎｉｃｓ Ｓｉｎｇａｐｏｒｅ Ｐｔｅ Ｌｔｄ． 半導体装置の製造方法と半導体装置
TWI685841B (zh) 2019-03-08 2020-02-21 華邦電子股份有限公司 動態隨機存取記憶體及其製造方法
TWI715335B (zh) * 2019-12-05 2021-01-01 華邦電子股份有限公司 記憶體結構及其形成方法
CN117320434A (zh) * 2022-06-13 2023-12-29 长鑫存储技术有限公司 一种半导体结构及其制作方法
JP7610613B2 (ja) * 2022-06-13 2025-01-08 チャンシン メモリー テクノロジーズ インコーポレイテッド 半導体構造及びその製作方法

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0287570A (ja) * 1988-09-25 1990-03-28 Sony Corp 半導体メモリ装置
JPH02198170A (ja) * 1989-01-27 1990-08-06 Hitachi Ltd 半導体集積回路装置及びその製造方法
JPH03187272A (ja) * 1989-12-15 1991-08-15 Mitsubishi Electric Corp Ｍｏｓ型電界効果トランジスタ及びその製造方法
JP3745392B2 (ja) * 1994-05-26 2006-02-15 株式会社ルネサステクノロジ 半導体装置
JP3371708B2 (ja) * 1996-08-22 2003-01-27 ソニー株式会社 縦型電界効果トランジスタの製造方法
US6218236B1 (en) 1999-01-28 2001-04-17 International Business Machines Corporation Method of forming a buried bitline in a vertical DRAM device
US20030093751A1 (en) * 2001-11-09 2003-05-15 David Hohl System and method for fast cyclic redundancy calculation
US7262089B2 (en) 2004-03-11 2007-08-28 Micron Technology, Inc. Methods of forming semiconductor structures
US7365385B2 (en) * 2004-08-30 2008-04-29 Micron Technology, Inc. DRAM layout with vertical FETs and method of formation
KR100618875B1 (ko) 2004-11-08 2006-09-04 삼성전자주식회사 수직 채널 ｍｏｓ 트랜지스터를 구비한 반도체 메모리소자 및 그 제조방법
KR100739532B1 (ko) * 2006-06-09 2007-07-13 삼성전자주식회사 매몰 비트라인 형성 방법
KR100759839B1 (ko) 2006-06-19 2007-09-18 삼성전자주식회사 수직 채널 반도체 장치 및 그 제조 방법
US7678654B2 (en) 2006-06-30 2010-03-16 Qimonda Ag Buried bitline with reduced resistance
US8058683B2 (en) * 2007-01-18 2011-11-15 Samsung Electronics Co., Ltd. Access device having vertical channel and related semiconductor device and a method of fabricating the access device
WO2009096001A1 (ja) * 2008-01-29 2009-08-06 Unisantis Electronics (Japan) Ltd. 半導体記憶装置およびメモリ混載半導体装置、並びにそれらの製造方法
KR100956601B1 (ko) * 2008-03-25 2010-05-11 주식회사 하이닉스반도체 반도체 소자의 수직 채널 트랜지스터 및 그 형성 방법
KR101394157B1 (ko) * 2008-04-08 2014-05-14 삼성전자주식회사 수직 필러 트랜지스터, 이를 포함하는 디램 소자, 수직필러 트랜지스터 형성 방법 및 반도체 박막 형성 방법.
KR101149043B1 (ko) * 2009-10-30 2012-05-24 에스케이하이닉스 주식회사 매립형 비트라인을 구비하는 반도체 장치 및 그 제조방법

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8836001B2 (en) 2012-03-19 2014-09-16 SK Hynix Inc. Semiconductor device having buried bit line, and method for fabricating the same

Also Published As

Publication number Publication date
US20110220977A1 (en) 2011-09-15
JP2011187927A (ja) 2011-09-22
JP5722600B2 (ja) 2015-05-20
US8373214B2 (en) 2013-02-12

Similar Documents

Publication Publication Date Title
KR20110101876A (ko) 매립 비트 라인을 갖는 반도체 장치 및 반도체 장치의 제조 방법
US10692879B2 (en) Semiconductor device including different orientations of memory cell array and peripheral circuit transistors
US9761593B2 (en) Semiconductor device
US8648423B2 (en) Semiconductor devices including buried-channel-array transistors
US8445954B2 (en) Three-dimensional semiconductor memory device
US7005328B2 (en) Non-volatile memory device
CN100388465C (zh) 半导体器件的制造方法
US9276074B2 (en) Methods of fabricating semiconductor devices having buried channel array
US6518124B1 (en) Method of fabricating semiconductor device
US8501606B2 (en) Methods of forming wiring structures
US8697570B2 (en) Semiconductor device including contact plug and method of manufacturing the same
US9536884B2 (en) Semiconductor device having positive fixed charge containing layer
US9640432B2 (en) Memory device structure and fabricating method thereof
US11257821B1 (en) Digit line and body contact for semiconductor devices
US20150079757A1 (en) Method of fabricating semiconductor device
US8642438B2 (en) Method of manufacturing an integrated circuit device
US8258517B2 (en) Semiconductor device having driving transistors
JP4773073B2 (ja) 半導体装置の製造方法
US20120238099A1 (en) Method of manufacturing electronic part
US9685451B2 (en) Nonvolatile memory device and method for fabricating the same
KR20120128518A (ko) 반도체 소자의 제조 방법
US20150311297A1 (en) Semiconductor device and method of forming thereof
US8492812B2 (en) Semiconductor device having dummy pattern and method of fabricating a semiconductor device comprising dummy pattern
US7332390B2 (en) Semiconductor memory device and fabrication thereof
US20070032006A1 (en) Fabrication method of flash memory

Legal Events

Date Code Title Description
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 20100310

PG1501 Laying open of application
A201 Request for examination
AMND Amendment
PA0201 Request for examination

Patent event code: PA02012R01D

Patent event date: 20150310

Comment text: Request for Examination of Application

Patent event code: PA02011R01I

Patent event date: 20100310

Comment text: Patent Application

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

Comment text: Notification of reason for refusal

Patent event date: 20160121

Patent event code: PE09021S01D

E601 Decision to refuse application
PE0601 Decision on rejection of patent

Patent event date: 20160729

Comment text: Decision to Refuse Application

Patent event code: PE06012S01D

Patent event date: 20160121

Comment text: Notification of reason for refusal

Patent event code: PE06011S01I

AMND Amendment
PX0901 Re-examination

Patent event code: PX09011S01I

Patent event date: 20160729

Comment text: Decision to Refuse Application

Patent event code: PX09012R01I

Patent event date: 20150310

Comment text: Amendment to Specification, etc.

PX0601 Decision of rejection after re-examination

Comment text: Decision to Refuse Application

Patent event code: PX06014S01D

Patent event date: 20160928

Comment text: Amendment to Specification, etc.

Patent event code: PX06012R01I

Patent event date: 20160826

Comment text: Decision to Refuse Application

Patent event code: PX06011S01I

Patent event date: 20160729

Comment text: Notification of reason for refusal

Patent event code: PX06013S01I

Patent event date: 20160121

Comment text: Amendment to Specification, etc.

Patent event code: PX06012R01I

Patent event date: 20150310