KR20110069664A - 순차 회로에서 누설 전류 감소 - Google Patents

순차 회로에서 누설 전류 감소 Download PDF

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Publication number
KR20110069664A
KR20110069664A KR1020100014991A KR20100014991A KR20110069664A KR 20110069664 A KR20110069664 A KR 20110069664A KR 1020100014991 A KR1020100014991 A KR 1020100014991A KR 20100014991 A KR20100014991 A KR 20100014991A KR 20110069664 A KR20110069664 A KR 20110069664A
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South Korea
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English (en)
Korean (ko)
Inventor
스리니바스 스리아디브하트라
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엘에스아이 코포레이션
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Publication of KR20110069664A publication Critical patent/KR20110069664A/ko
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/012—Modifications of generator to improve response time or to decrease power consumption
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Power Sources (AREA)
KR1020100014991A 2009-12-17 2010-02-19 순차 회로에서 누설 전류 감소 Withdrawn KR20110069664A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/640,004 US8736332B2 (en) 2009-12-17 2009-12-17 Leakage current reduction in a sequential circuit
US12/640,004 2009-12-17

Publications (1)

Publication Number Publication Date
KR20110069664A true KR20110069664A (ko) 2011-06-23

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020100014991A Withdrawn KR20110069664A (ko) 2009-12-17 2010-02-19 순차 회로에서 누설 전류 감소

Country Status (6)

Country Link
US (1) US8736332B2 (enExample)
EP (1) EP2339752B1 (enExample)
JP (1) JP5462703B2 (enExample)
KR (1) KR20110069664A (enExample)
CN (1) CN101777908A (enExample)
TW (1) TW201123731A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160079402A (ko) * 2014-12-26 2016-07-06 전자부품연구원 저전력 구현을 위한 순차회로 설계방법 및 그 방법에 사용되는 클럭 게이팅 회로

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8307226B1 (en) * 2011-12-20 2012-11-06 Intel Corporation Method, apparatus, and system for reducing leakage power consumption
US9100002B2 (en) 2013-09-12 2015-08-04 Micron Technology, Inc. Apparatus and methods for leakage current reduction in integrated circuits
US9496851B2 (en) * 2014-09-10 2016-11-15 Qualcomm Incorporated Systems and methods for setting logic to a desired leakage state
US9601477B2 (en) * 2014-12-18 2017-03-21 Marvell World Trade Ltd. Integrated circuit having spare circuit cells
US9503086B1 (en) * 2015-09-16 2016-11-22 Apple Inc. Lockup latch for subthreshold operation
CN105515565B (zh) * 2015-12-14 2018-07-13 天津光电通信技术有限公司 一种硬件逻辑资源复用模块及复用实现的方法
US10423203B2 (en) * 2016-12-28 2019-09-24 Intel Corporation Flip-flop circuit with low-leakage transistors

Family Cites Families (13)

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Publication number Priority date Publication date Assignee Title
TW392307B (en) * 1998-01-13 2000-06-01 Mitsubishi Electric Corp A method of the manufacture and the setup of the semiconductor apparatus
JPH11340812A (ja) 1998-05-22 1999-12-10 Mitsubishi Electric Corp 半導体装置
US6169419B1 (en) * 1998-09-10 2001-01-02 Intel Corporation Method and apparatus for reducing standby leakage current using a transistor stack effect
US6191606B1 (en) 1998-09-10 2001-02-20 Intel Corporation Method and apparatus for reducing standby leakage current using input vector activation
US7302652B2 (en) * 2003-03-31 2007-11-27 Intel Corporation Leakage control in integrated circuits
US7096374B2 (en) * 2003-05-21 2006-08-22 Agilent Technologies, Inc. Method and apparatus for defining an input state vector that achieves low power consumption in digital circuit in an idle state
KR100574967B1 (ko) 2004-01-29 2006-04-28 삼성전자주식회사 Ｍｔｃｍｏｓ용 제어회로
US7305335B2 (en) * 2004-11-23 2007-12-04 Schweitzer Engineering Laboratories, Inc. Permanent three-pole independent pole operation recloser simulator feature in a single-pole trip capable recloser control
US20070168792A1 (en) * 2005-12-09 2007-07-19 International Business Machines Corporation Method to Reduce Leakage Within a Sequential Network and Latch Circuit
JP4953716B2 (ja) * 2006-07-25 2012-06-13 パナソニック株式会社 半導体集積回路およびその関連技術
US7949971B2 (en) * 2007-03-27 2011-05-24 International Business Machines Corporation Method and apparatus for on-the-fly minimum power state transition
GB2447944B (en) 2007-03-28 2011-06-29 Advanced Risc Mach Ltd Reducing leakage power in low power mode
US7735045B1 (en) * 2008-03-12 2010-06-08 Xilinx, Inc. Method and apparatus for mapping flip-flop logic onto shift register logic

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160079402A (ko) * 2014-12-26 2016-07-06 전자부품연구원 저전력 구현을 위한 순차회로 설계방법 및 그 방법에 사용되는 클럭 게이팅 회로

Also Published As

Publication number Publication date
JP2011130405A (ja) 2011-06-30
EP2339752B1 (en) 2014-05-21
TW201123731A (en) 2011-07-01
EP2339752A1 (en) 2011-06-29
JP5462703B2 (ja) 2014-04-02
CN101777908A (zh) 2010-07-14
US20110148496A1 (en) 2011-06-23
US8736332B2 (en) 2014-05-27

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PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 20100219

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid