TW201123731A - Leakage current reduction in a sequential circuit - Google Patents
Leakage current reduction in a sequential circuit Download PDFInfo
- Publication number
- TW201123731A TW201123731A TW099116527A TW99116527A TW201123731A TW 201123731 A TW201123731 A TW 201123731A TW 099116527 A TW099116527 A TW 099116527A TW 99116527 A TW99116527 A TW 99116527A TW 201123731 A TW201123731 A TW 201123731A
- Authority
- TW
- Taiwan
- Prior art keywords
- flop
- reset flip
- reset
- flip
- circuit
- Prior art date
Links
- 230000001960 triggered effect Effects 0.000 claims abstract description 22
- 230000001360 synchronised effect Effects 0.000 claims description 23
- 238000000034 method Methods 0.000 claims description 18
- 238000013461 design Methods 0.000 description 4
- 230000002441 reversible effect Effects 0.000 description 4
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 241000338137 Teratosphaeria nubilosa Species 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000003786 synthesis reaction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0008—Arrangements for reducing power consumption
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/012—Modifications of generator to improve response time or to decrease power consumption
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Power Sources (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/640,004 US8736332B2 (en) | 2009-12-17 | 2009-12-17 | Leakage current reduction in a sequential circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW201123731A true TW201123731A (en) | 2011-07-01 |
Family
ID=42514259
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW099116527A TW201123731A (en) | 2009-12-17 | 2010-05-24 | Leakage current reduction in a sequential circuit |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US8736332B2 (enExample) |
| EP (1) | EP2339752B1 (enExample) |
| JP (1) | JP5462703B2 (enExample) |
| KR (1) | KR20110069664A (enExample) |
| CN (1) | CN101777908A (enExample) |
| TW (1) | TW201123731A (enExample) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8307226B1 (en) * | 2011-12-20 | 2012-11-06 | Intel Corporation | Method, apparatus, and system for reducing leakage power consumption |
| US9100002B2 (en) | 2013-09-12 | 2015-08-04 | Micron Technology, Inc. | Apparatus and methods for leakage current reduction in integrated circuits |
| US9496851B2 (en) * | 2014-09-10 | 2016-11-15 | Qualcomm Incorporated | Systems and methods for setting logic to a desired leakage state |
| US9601477B2 (en) * | 2014-12-18 | 2017-03-21 | Marvell World Trade Ltd. | Integrated circuit having spare circuit cells |
| KR101971472B1 (ko) * | 2014-12-26 | 2019-08-13 | 전자부품연구원 | 저전력 구현을 위한 순차회로 설계방법 |
| US9503086B1 (en) * | 2015-09-16 | 2016-11-22 | Apple Inc. | Lockup latch for subthreshold operation |
| CN105515565B (zh) * | 2015-12-14 | 2018-07-13 | 天津光电通信技术有限公司 | 一种硬件逻辑资源复用模块及复用实现的方法 |
| US10423203B2 (en) * | 2016-12-28 | 2019-09-24 | Intel Corporation | Flip-flop circuit with low-leakage transistors |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW392307B (en) * | 1998-01-13 | 2000-06-01 | Mitsubishi Electric Corp | A method of the manufacture and the setup of the semiconductor apparatus |
| JPH11340812A (ja) | 1998-05-22 | 1999-12-10 | Mitsubishi Electric Corp | 半導体装置 |
| US6169419B1 (en) * | 1998-09-10 | 2001-01-02 | Intel Corporation | Method and apparatus for reducing standby leakage current using a transistor stack effect |
| US6191606B1 (en) | 1998-09-10 | 2001-02-20 | Intel Corporation | Method and apparatus for reducing standby leakage current using input vector activation |
| US7302652B2 (en) * | 2003-03-31 | 2007-11-27 | Intel Corporation | Leakage control in integrated circuits |
| US7096374B2 (en) * | 2003-05-21 | 2006-08-22 | Agilent Technologies, Inc. | Method and apparatus for defining an input state vector that achieves low power consumption in digital circuit in an idle state |
| KR100574967B1 (ko) | 2004-01-29 | 2006-04-28 | 삼성전자주식회사 | Ｍｔｃｍｏｓ용 제어회로 |
| US7305335B2 (en) * | 2004-11-23 | 2007-12-04 | Schweitzer Engineering Laboratories, Inc. | Permanent three-pole independent pole operation recloser simulator feature in a single-pole trip capable recloser control |
| US20070168792A1 (en) * | 2005-12-09 | 2007-07-19 | International Business Machines Corporation | Method to Reduce Leakage Within a Sequential Network and Latch Circuit |
| JP4953716B2 (ja) * | 2006-07-25 | 2012-06-13 | パナソニック株式会社 | 半導体集積回路およびその関連技術 |
| US7949971B2 (en) * | 2007-03-27 | 2011-05-24 | International Business Machines Corporation | Method and apparatus for on-the-fly minimum power state transition |
| GB2447944B (en) | 2007-03-28 | 2011-06-29 | Advanced Risc Mach Ltd | Reducing leakage power in low power mode |
| US7735045B1 (en) * | 2008-03-12 | 2010-06-08 | Xilinx, Inc. | Method and apparatus for mapping flip-flop logic onto shift register logic |
-
2009
- 2009-12-17 US US12/640,004 patent/US8736332B2/en active Active
-
2010
- 2010-02-11 CN CN201010109303.9A patent/CN101777908A/zh active Pending
- 2010-02-19 KR KR1020100014991A patent/KR20110069664A/ko not_active Withdrawn
- 2010-03-30 EP EP10158485.2A patent/EP2339752B1/en not_active Not-in-force
- 2010-05-13 JP JP2010111048A patent/JP5462703B2/ja not_active Expired - Fee Related
- 2010-05-24 TW TW099116527A patent/TW201123731A/zh unknown
Also Published As
| Publication number | Publication date |
|---|---|
| JP2011130405A (ja) | 2011-06-30 |
| EP2339752B1 (en) | 2014-05-21 |
| EP2339752A1 (en) | 2011-06-29 |
| JP5462703B2 (ja) | 2014-04-02 |
| CN101777908A (zh) | 2010-07-14 |
| US20110148496A1 (en) | 2011-06-23 |
| US8736332B2 (en) | 2014-05-27 |
| KR20110069664A (ko) | 2011-06-23 |
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