KR20110018700A - 비오씨 반도체 패키지 기판의 제조방법 및 비오씨 반도체 패키지 기판 - Google Patents
비오씨 반도체 패키지 기판의 제조방법 및 비오씨 반도체 패키지 기판 Download PDFInfo
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- KR20110018700A KR20110018700A KR1020090076297A KR20090076297A KR20110018700A KR 20110018700 A KR20110018700 A KR 20110018700A KR 1020090076297 A KR1020090076297 A KR 1020090076297A KR 20090076297 A KR20090076297 A KR 20090076297A KR 20110018700 A KR20110018700 A KR 20110018700A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 131
- 238000007747 plating Methods 0.000 claims abstract description 122
- 229910052737 gold Inorganic materials 0.000 claims abstract description 34
- 239000010931 gold Substances 0.000 claims abstract description 34
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 31
- 229910000679 solder Inorganic materials 0.000 claims abstract description 28
- 239000004065 semiconductor Substances 0.000 claims abstract description 23
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims description 55
- 238000000034 method Methods 0.000 claims description 50
- 238000009713 electroplating Methods 0.000 claims description 5
- 239000007788 liquid Substances 0.000 claims description 4
- 229910052709 silver Inorganic materials 0.000 claims description 4
- 229910052804 chromium Inorganic materials 0.000 claims description 3
- 229910052745 lead Inorganic materials 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 229910052763 palladium Inorganic materials 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 230000002950 deficient Effects 0.000 abstract 1
- 230000035515 penetration Effects 0.000 abstract 1
- 230000007547 defect Effects 0.000 description 4
- 238000005538 encapsulation Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000000047 product Substances 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005553 drilling Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000001035 drying Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
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- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D17/00—Constructional parts, or assemblies thereof, of cells for electrolytic coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Chemical & Material Sciences (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Electrochemistry (AREA)
- Materials Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Wire Bonding (AREA)
Abstract
Description
Claims (11)
- 기판상에 가공된 도통홀을 도금처리하는 1단계;상기 기판의 중앙부위의 원도우부를 제외한 영역에 본딩패드, 솔더볼패드 및 도금인입선을 포함하는 회로패턴을 형성하는 2단계;상기 기판에 금도금을 수행하는 3단계;를 포함하는 것을 특징으로 하는 비오씨 반도체 패키지 기판의 제조방법.
- 청구항 1에 있어서,상기 1단계는,상기 도금처리는 Ni, Cr, Au, Ag, Pb, Pd 중 선택되는 어느 하나를 이용하여 형성하는 단계인 것을 특징으로 하는 비오씨 반도체 패키지 기판의 제조방법.
- 청구항 1에 있어서,상기 2단계는,상기 원도우부를 제외한 영역에 형성되는 도금인입선은,상기 기판의 후면에 적어도 1 이상 형성하는 단계인 것을 특징으로 하는 비오씨 반도체 패키지 기판의 제조방법.
- 청구항 3에 있어서,상기 2단계의 회로패턴의 형성은 기판상에 드라이필름레지스트(DFR)을 도포하여 노광, 현상을 통해 구현하는 것을 특징으로 하는 비오시 반도체 패키지 기판의 제조방법.
- 청구항 3에 있어서,상기 도금인입선은 상기 기판에 형성되는 도통홀과 적어도 1 이상 연결되는 것을 특징으로 하는 비오씨 반도체 패키지 기판의 제조방법.
- 청구항 1에 있어서,상기 3단계는,상기 기판의 전 후면에 전기 금도금을 수행하되,상기 기판의 전면의 도금 부위 중 일부는 기판 후면에 형성된 도금인입선과 연결된 도통홀을 통해 도금액이 기판의 전면으로 이동하여 도금패턴을 형성하는 방식으로 수행되는 것을 특징으로 하는 비오씨 반도체 패키지 기판의 제조방법.
- 청구항 1에 있어서,상기 2단계 이후에 회로패턴을 제외한 영역에 솔더레지시트(Solder resist)를 도포하는 단계를 더 포함하는 것을 특징으로 하는 비오씨 반도체 패키지 기판의 제조방법.
- 비오씨(BOC;Board of chip) 반도체 패키지 기판에 있어서,기판의 중심부에 와이어 본딩을 위해 기판 면이 노출되도록 형성되는 윈도우부;상기 윈도우부를 제외한 영역에 형성되는 전도성 회로패턴 및 도금인입선;을 포함하는 비오씨 반도체 패키지 기판.
- 청구항 8에 있어서,상기 기판은,적어도 1 이상의 부위에 형성되는 도통홀을 포함하며,상기 도금인입선은 상기 기판의 후면에 상기 도통홀과 연결되는 구조로 적어도 1 이상 형성되는 것을 특징으로 하는 비오씨 반도체 패키지 기판.
- 청구항 9에 있어서,상기 회로패턴은 본딩패드 및 솔더볼패드에 형성되는 금도금층;상기 금도금층은 상기 기판의 후면에 형성되는 도금인입선과 적어도 1이상은 연결되는 구조로 형성되는 비오씨 반도체 패키지 기판.
- 청구항 8 내지 10 중 어느 한항에 있어서,상기 윈도우부은, 상기 윈도우부의 절단면으로부터 윈도우부 중심면으로 돌출되는 도금패턴이 0.001 이상 0.1um 이하인 것을 특징으로 하는 비오씨 반도체 패키지 기판.
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