KR20100084164A - Nvm 회로를 논리 회로와 통합하는 방법 - Google Patents
Nvm 회로를 논리 회로와 통합하는 방법 Download PDFInfo
- Publication number
- KR20100084164A KR20100084164A KR1020107009304A KR20107009304A KR20100084164A KR 20100084164 A KR20100084164 A KR 20100084164A KR 1020107009304 A KR1020107009304 A KR 1020107009304A KR 20107009304 A KR20107009304 A KR 20107009304A KR 20100084164 A KR20100084164 A KR 20100084164A
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- South Korea
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- sacrificial layers
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
- H10P95/06—Planarisation of inorganic insulating materials
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
- H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
- H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
- H10B41/44—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a control gate layer also being used as part of the peripheral transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
- H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
- H10B41/48—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a tunnel dielectric layer also being used as part of the peripheral transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0411—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having floating gates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0413—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having charge-trapping gate insulators, e.g. MNOS transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/68—Floating-gate IGFETs
- H10D30/681—Floating-gate IGFETs having only two programming levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/68—Floating-gate IGFETs
- H10D30/6891—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode
- H10D30/6892—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/68—Floating-gate IGFETs
- H10D30/6891—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode
- H10D30/6893—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode wherein the floating gate has multiple non-connected parts, e.g. multi-particle floating gate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
- H10D30/694—IGFETs having charge trapping gate insulators, e.g. MNOS transistors characterised by the shapes, relative sizes or dispositions of the gate electrodes
- H10D30/696—IGFETs having charge trapping gate insulators, e.g. MNOS transistors characterised by the shapes, relative sizes or dispositions of the gate electrodes having at least one additional gate, e.g. program gate, erase gate or select gate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/031—Manufacture or treatment of data-storage electrodes
- H10D64/035—Manufacture or treatment of data-storage electrodes comprising conductor-insulator-conductor-insulator-semiconductor structures
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/031—Manufacture or treatment of data-storage electrodes
- H10D64/037—Manufacture or treatment of data-storage electrodes comprising charge-trapping insulators
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Nanotechnology (AREA)
- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Theoretical Computer Science (AREA)
- Crystallography & Structural Chemistry (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/926,348 | 2007-10-29 | ||
| US11/926,348 US7745344B2 (en) | 2007-10-29 | 2007-10-29 | Method for integrating NVM circuitry with logic circuitry |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20100084164A true KR20100084164A (ko) | 2010-07-23 |
Family
ID=40583356
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020107009304A Withdrawn KR20100084164A (ko) | 2007-10-29 | 2008-09-18 | Nvm 회로를 논리 회로와 통합하는 방법 |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US7745344B2 (enExample) |
| EP (1) | EP2206151B1 (enExample) |
| JP (1) | JP2011502353A (enExample) |
| KR (1) | KR20100084164A (enExample) |
| CN (1) | CN101842899B (enExample) |
| AT (1) | ATE554501T1 (enExample) |
| TW (1) | TWI437667B (enExample) |
| WO (1) | WO2009058486A1 (enExample) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20120021271A (ko) * | 2010-08-31 | 2012-03-08 | 프리스케일 세미컨덕터, 인크. | 비-휘발성 메모리(nvm) 영역의 동시 에칭을 동반한 비휘발성 메모리(nvm)의 게이트 스택 패터닝 |
Families Citing this family (37)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010067645A (ja) * | 2008-09-08 | 2010-03-25 | Renesas Technology Corp | 半導体装置およびその製造方法 |
| FR2959349B1 (fr) * | 2010-04-22 | 2012-09-21 | Commissariat Energie Atomique | Fabrication d'une memoire a deux grilles independantes auto-alignees |
| US8399310B2 (en) | 2010-10-29 | 2013-03-19 | Freescale Semiconductor, Inc. | Non-volatile memory and logic circuit process integration |
| US8658497B2 (en) | 2012-01-04 | 2014-02-25 | Freescale Semiconductor, Inc. | Non-volatile memory (NVM) and logic integration |
| US8669158B2 (en) | 2012-01-04 | 2014-03-11 | Mark D. Hall | Non-volatile memory (NVM) and logic integration |
| US8906764B2 (en) | 2012-01-04 | 2014-12-09 | Freescale Semiconductor, Inc. | Non-volatile memory (NVM) and logic integration |
| US8951863B2 (en) | 2012-04-06 | 2015-02-10 | Freescale Semiconductor, Inc. | Non-volatile memory (NVM) and logic integration |
| US8722493B2 (en) | 2012-04-09 | 2014-05-13 | Freescale Semiconductor, Inc. | Logic transistor and non-volatile memory cell integration |
| US9087913B2 (en) | 2012-04-09 | 2015-07-21 | Freescale Semiconductor, Inc. | Integration technique using thermal oxide select gate dielectric for select gate and apartial replacement gate for logic |
| US8728886B2 (en) | 2012-06-08 | 2014-05-20 | Freescale Semiconductor, Inc. | Integrating formation of a replacement gate transistor and a non-volatile memory cell using a high-k dielectric |
| TWI485811B (zh) * | 2012-07-18 | 2015-05-21 | 鉅晶電子股份有限公司 | 半導體結構的製造方法 |
| US9111865B2 (en) * | 2012-10-26 | 2015-08-18 | Freescale Semiconductor, Inc. | Method of making a logic transistor and a non-volatile memory (NVM) cell |
| JP6026914B2 (ja) * | 2013-02-12 | 2016-11-16 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
| US8716089B1 (en) | 2013-03-08 | 2014-05-06 | Freescale Semiconductor, Inc. | Integrating formation of a replacement gate transistor and a non-volatile memory cell having thin film storage |
| US8741719B1 (en) | 2013-03-08 | 2014-06-03 | Freescale Semiconductor, Inc. | Integrating formation of a logic transistor and a non-volatile memory cell using a partial replacement gate technique |
| US9006093B2 (en) | 2013-06-27 | 2015-04-14 | Freescale Semiconductor, Inc. | Non-volatile memory (NVM) and high voltage transistor integration |
| CN104347514B (zh) * | 2013-07-30 | 2017-08-01 | 中芯国际集成电路制造(上海)有限公司 | 一种嵌入式闪存的制作方法 |
| US8871598B1 (en) | 2013-07-31 | 2014-10-28 | Freescale Semiconductor, Inc. | Non-volatile memory (NVM) and high-k and metal gate integration using gate-first methodology |
| US9129996B2 (en) | 2013-07-31 | 2015-09-08 | Freescale Semiconductor, Inc. | Non-volatile memory (NVM) cell and high-K and metal gate transistor integration |
| US8877585B1 (en) | 2013-08-16 | 2014-11-04 | Freescale Semiconductor, Inc. | Non-volatile memory (NVM) cell, high voltage transistor, and high-K and metal gate transistor integration |
| US9082837B2 (en) | 2013-08-08 | 2015-07-14 | Freescale Semiconductor, Inc. | Nonvolatile memory bitcell with inlaid high k metal select gate |
| US9252246B2 (en) | 2013-08-21 | 2016-02-02 | Freescale Semiconductor, Inc. | Integrated split gate non-volatile memory cell and logic device |
| US9082650B2 (en) | 2013-08-21 | 2015-07-14 | Freescale Semiconductor, Inc. | Integrated split gate non-volatile memory cell and logic structure |
| US9275864B2 (en) | 2013-08-22 | 2016-03-01 | Freescale Semiconductor,Inc. | Method to form a polysilicon nanocrystal thin film storage bitcell within a high k metal gate platform technology using a gate last process to form transistor gates |
| US8932925B1 (en) * | 2013-08-22 | 2015-01-13 | Freescale Semiconductor, Inc. | Split-gate non-volatile memory (NVM) cell and device structure integration |
| US9129855B2 (en) | 2013-09-30 | 2015-09-08 | Freescale Semiconductor, Inc. | Non-volatile memory (NVM) and high-k and metal gate integration using gate-first methodology |
| US9136129B2 (en) | 2013-09-30 | 2015-09-15 | Freescale Semiconductor, Inc. | Non-volatile memory (NVM) and high-k and metal gate integration using gate-last methodology |
| US8901632B1 (en) | 2013-09-30 | 2014-12-02 | Freescale Semiconductor, Inc. | Non-volatile memory (NVM) and high-K and metal gate integration using gate-last methodology |
| US9231077B2 (en) | 2014-03-03 | 2016-01-05 | Freescale Semiconductor, Inc. | Method of making a logic transistor and non-volatile memory (NVM) cell |
| US9112056B1 (en) | 2014-03-28 | 2015-08-18 | Freescale Semiconductor, Inc. | Method for forming a split-gate device |
| US9472418B2 (en) | 2014-03-28 | 2016-10-18 | Freescale Semiconductor, Inc. | Method for forming a split-gate device |
| US9252152B2 (en) | 2014-03-28 | 2016-02-02 | Freescale Semiconductor, Inc. | Method for forming a split-gate device |
| US9257445B2 (en) * | 2014-05-30 | 2016-02-09 | Freescale Semiconductor, Inc. | Method of making a split gate non-volatile memory (NVM) cell and a logic transistor |
| US9379222B2 (en) | 2014-05-30 | 2016-06-28 | Freescale Semiconductor, Inc. | Method of making a split gate non-volatile memory (NVM) cell |
| US9343314B2 (en) | 2014-05-30 | 2016-05-17 | Freescale Semiconductor, Inc. | Split gate nanocrystal memory integration |
| CN105336698B (zh) * | 2014-07-10 | 2018-11-16 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件的制造方法 |
| US10134748B2 (en) | 2016-11-29 | 2018-11-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Cell boundary structure for embedded memory |
Family Cites Families (24)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2664685B2 (ja) * | 1987-07-31 | 1997-10-15 | 株式会社東芝 | 半導体装置の製造方法 |
| JP3107199B2 (ja) | 1996-08-29 | 2000-11-06 | 日本電気株式会社 | 不揮発性半導体記憶装置の製造方法 |
| US6236101B1 (en) * | 1997-11-05 | 2001-05-22 | Texas Instruments Incorporated | Metallization outside protective overcoat for improved capacitors and inductors |
| US6271143B1 (en) * | 1999-05-06 | 2001-08-07 | Motorola, Inc. | Method for preventing trench fill erosion |
| US6323047B1 (en) | 1999-08-03 | 2001-11-27 | Advanced Micro Devices, Inc. | Method for monitoring second gate over-etch in a semiconductor device |
| KR100555485B1 (ko) | 1999-09-13 | 2006-03-03 | 삼성전자주식회사 | 플래쉬 메모리 소자의 제조방법 |
| JP4096507B2 (ja) * | 2000-09-29 | 2008-06-04 | 富士通株式会社 | 半導体装置の製造方法 |
| US6559059B2 (en) | 2001-01-19 | 2003-05-06 | United Microelectronics Corp. | Method for fabricating a MOS transistor of an embedded memory |
| US6509235B2 (en) | 2001-01-19 | 2003-01-21 | United Microelectronics Corp. | Method for making an embedded memory MOS |
| US6531350B2 (en) | 2001-02-22 | 2003-03-11 | Halo, Inc. | Twin MONOS cell fabrication method and array organization |
| US6808974B2 (en) * | 2001-05-15 | 2004-10-26 | International Business Machines Corporation | CMOS structure with maximized polysilicon gate activation and a method for selectively maximizing doping activation in gate, extension, and source/drain regions |
| US6818504B2 (en) * | 2001-08-10 | 2004-11-16 | Hynix Semiconductor America, Inc. | Processes and structures for self-aligned contact non-volatile memory with peripheral transistors easily modifiable for various technologies and applications |
| US6753242B2 (en) | 2002-03-19 | 2004-06-22 | Motorola, Inc. | Integrated circuit device and method therefor |
| US6875622B1 (en) * | 2002-11-01 | 2005-04-05 | Advanced Micro Devices, Inc. | Method and apparatus for determining electromagnetic properties of a process layer using scatterometry measurements |
| KR100500448B1 (ko) * | 2003-02-06 | 2005-07-14 | 삼성전자주식회사 | 선택적 디스포저블 스페이서 기술을 사용하는 반도체집적회로의 제조방법 및 그에 의해 제조된 반도체 집적회로 |
| JP4477886B2 (ja) * | 2003-04-28 | 2010-06-09 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
| CN100464429C (zh) * | 2003-10-28 | 2009-02-25 | 株式会社半导体能源研究所 | 液晶显示设备及其制造方法,以及液晶电视接收机 |
| US6964902B2 (en) | 2004-02-26 | 2005-11-15 | Freescale Semiconductor, Inc. | Method for removing nanoclusters from selected regions |
| US7361543B2 (en) * | 2004-11-12 | 2008-04-22 | Freescale Semiconductor, Inc. | Method of forming a nanocluster charge storage device |
| US7151302B1 (en) | 2005-06-24 | 2006-12-19 | Freescale Semiconductor, Inc. | Method and apparatus for maintaining topographical uniformity of a semiconductor memory array |
| US7361551B2 (en) * | 2006-02-16 | 2008-04-22 | Freescale Semiconductor, Inc. | Method for making an integrated circuit having an embedded non-volatile memory |
| US7700439B2 (en) * | 2006-03-15 | 2010-04-20 | Freescale Semiconductor, Inc. | Silicided nonvolatile memory and method of making same |
| JP2007281348A (ja) * | 2006-04-11 | 2007-10-25 | Renesas Technology Corp | 半導体装置およびその製造方法 |
| JP2009049338A (ja) * | 2007-08-23 | 2009-03-05 | Toshiba Corp | 半導体装置及びその製造方法 |
-
2007
- 2007-10-29 US US11/926,348 patent/US7745344B2/en active Active
-
2008
- 2008-09-18 WO PCT/US2008/076750 patent/WO2009058486A1/en not_active Ceased
- 2008-09-18 AT AT08844581T patent/ATE554501T1/de active
- 2008-09-18 KR KR1020107009304A patent/KR20100084164A/ko not_active Withdrawn
- 2008-09-18 JP JP2010531101A patent/JP2011502353A/ja active Pending
- 2008-09-18 EP EP08844581A patent/EP2206151B1/en active Active
- 2008-09-18 CN CN2008801140238A patent/CN101842899B/zh active Active
- 2008-10-01 TW TW097137798A patent/TWI437667B/zh active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20120021271A (ko) * | 2010-08-31 | 2012-03-08 | 프리스케일 세미컨덕터, 인크. | 비-휘발성 메모리(nvm) 영역의 동시 에칭을 동반한 비휘발성 메모리(nvm)의 게이트 스택 패터닝 |
Also Published As
| Publication number | Publication date |
|---|---|
| US20090111226A1 (en) | 2009-04-30 |
| ATE554501T1 (de) | 2012-05-15 |
| CN101842899B (zh) | 2012-08-29 |
| TW200939404A (en) | 2009-09-16 |
| CN101842899A (zh) | 2010-09-22 |
| EP2206151A4 (en) | 2010-11-24 |
| WO2009058486A1 (en) | 2009-05-07 |
| EP2206151A1 (en) | 2010-07-14 |
| EP2206151B1 (en) | 2012-04-18 |
| JP2011502353A (ja) | 2011-01-20 |
| TWI437667B (zh) | 2014-05-11 |
| US7745344B2 (en) | 2010-06-29 |
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