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  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
  • H01L21/3105—After-treatment
  • H01L21/31051—Planarisation of the insulating layers
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  • B82—NANOTECHNOLOGY
  • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
  • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
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  • H10B41/42—Simultaneous manufacture of periphery and memory cells
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  • H10B41/42—Simultaneous manufacture of periphery and memory cells
  • H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
  • H10B41/44—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a control gate layer also being used as part of the peripheral transistor
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  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
  • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
  • H10B41/42—Simultaneous manufacture of periphery and memory cells
  • H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
  • H10B41/48—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a tunnel dielectric layer also being used as part of the peripheral transistor
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  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
  • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
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  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
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  • H10D30/01—Manufacture or treatment
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  • H10D30/0413—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having charge-trapping gate insulators, e.g. MNOS transistors
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  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/68—Floating-gate IGFETs
  • H10D30/681—Floating-gate IGFETs having only two programming levels
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  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/68—Floating-gate IGFETs
  • H10D30/6891—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode
  • H10D30/6892—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
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  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/68—Floating-gate IGFETs
  • H10D30/6891—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode
  • H10D30/6893—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode wherein the floating gate has multiple non-connected parts, e.g. multi-particle floating gate
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  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
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  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
  • H10D30/694—IGFETs having charge trapping gate insulators, e.g. MNOS transistors characterised by the shapes, relative sizes or dispositions of the gate electrodes
  • H10D30/696—IGFETs having charge trapping gate insulators, e.g. MNOS transistors characterised by the shapes, relative sizes or dispositions of the gate electrodes having at least one additional gate, e.g. program gate, erase gate or select gate
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  • H10D64/01—Manufacture or treatment
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  • H10D64/035—Manufacture or treatment of data-storage electrodes comprising conductor-insulator-conductor-insulator-semiconductor structures
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  • H10D64/01—Manufacture or treatment
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  • H10D64/037—Manufacture or treatment of data-storage electrodes comprising charge-trapping insulators

Definitions

• This disclosure relates generally to integrated circuit fabrication, and more specifically, to integrating Non-Volatile Memory (NVM) circuitry with logic circuitry in fabricating integrated circuit designs.
• NVM Non-Volatile Memory
• SoC System-on-chip
• SoC refers to devices that integrate several types of blocks, including logic, programmable parts, I/O, volatile memory and non-volatile memory on a single integrated circuit.
• Floating-gate based memories are frequently used as non-volatile memories in SoC designs.
• TFS thin film storage
• charge is stored in a thin insulating film consisting of silicon crystals commonly known as nanocrystals.
• TFS Thin Film Semiconductor
• logic circuitry in an SoC requires two gate etches, one for a select gate in the TFS area and another for the gate of logic or peripheral transistors in the logic area.
• the logic or peripheral transistors are very small, having critical dimensions, and are thus complicated to pattern.
• gates of tiny transistors are patterned using a bottom anti-reflective coating (BARC) layer which is deposited over the gate oxide to achieve critical dimension (CD) control of gate dimensions of the transistors. Since a BARC has high viscosity, it is difficult to deposit BARC layers. Further, the process gets more complicated if there is a difference in height between the memory area and logic area on the SoC.
• BARC bottom anti-reflective coating
• Another approach for patterning a small-dimensioned transistor includes deposition of a regular anti-reflective coating (ARC) or nitride. However, it is difficult to etch it in the later processes due to the non-planarity problem.
• ARC anti-reflective coating
• FIG. 1 illustrates a cross-section of a portion of a semiconductor device with a layer of dielectric material and a layer of gate material overlying the substrate, in accordance with an embodiment of the present invention
• FIG. 2 illustrates the semiconductor device of FIG. 1 after depositing multiple adjoining sacrificial layers, in accordance with an embodiment of the present invention
• FIG. 3 illustrates the semiconductor device of FIG. 2 after depositing a patterned photoresist layer, in accordance with an embodiment of the present invention
• FIG. 4 illustrates the semiconductor device of FIG. 3 after etching of the sacrificial layers and the first layer of gate material, in accordance with an embodiment of the present invention
• FIG. 5 illustrates the semiconductor device of FIG. 4 after the deposition of a charge storage stack above the sacrificial layers, in accordance with an embodiment of the present invention
• FIG. 6 illustrates the semiconductor device of FIG. 5 after depositing a second layer of gate material, in accordance with an embodiment of the present invention
• FIG. 7 illustrates the semiconductor device of FIG. 6 after polishing through the second layer of gate material till the polishing stop layer, in accordance with an embodiment of the present invention
• FIG. 12 illustrates the semiconductor device of FIG. 1 1 after the deposition of a photoresist mask for patterning a gate of a logic transistor in a logic area, in accordance with an embodiment of the present invention
• FIG. 13 illustrates the final processing steps for the formation of a memory transistor in a memory area and a logic transistor in a logic area, in accordance with an embodiment of the present invention.
• a method provides a substrate having a first defined area and a second defined area that are electrically separated from each other.
• the method provides a first layer of gate material overlying the substrate in both the first defined area and the second defined area.
• the method provides multiple adjoining sacrificial layers overlying the first layer of gate material.
• the method further uses the multiple adjoining sacrificial layers to form transistor control electrodes in the first defined area in which at least one of the adjoining sacrificial layers is not completely removed.
• the method uses one of the adjoining sacrificial layers to pattern transistor control electrode in the second defined area.
• the method completes formation of transistors in both the first defined area and the second defined area.
• a method of forming an integrated circuit includes a first region and a second region formed over a substrate and is separated by an isolation region.
• the method includes forming a first gate electrode material layer overlying the substrate in both the first region and the second region. Further, the method forms a plurality of sacrificial layers overlying the first gate electrode material layer in both the first region and the second region before forming any devices in the first region and the second region.
• the method includes using the plurality of sacrificial layers to form a first type of device in the first region.
• the method includes using the plurality of sacrificial layers to form a second type of device in the second region.
• a method of forming an integrated circuit includes a memory region and a logic region formed over a substrate and separated by an isolation region.
• the method includes forming a first gate electrode material layer overlying the substrate in both the memory region and the logic region.
• the method further includes forming a plurality of sacrificial layers overlying the first gate electrode material layer in both the memory region and the logic region prior to forming any device in the memory region and the logic region.
• the method includes using the plurality of sacrificial layers to form a non-volatile memory device in the memory region.
• the method includes using at least one of the plurality of sacrificial layers to form a logic device in the logic region.
• At least one of the plurality of sacrificial layers used to form the logic device is an anti-reflective coating (ARC) layer used to pattern a gate electrode corresponding to the logic device in the logic region.
• ARC anti-reflective coating
• FIGs. 1 - 13 illustrate a cross section of a portion of a semiconductor wafer during stages in the integration of Non-Volatile Memory (NVM) circuitry with logic circuitry, according to various embodiments of the present invention.
• NVM Non-Volatile Memory
• FIG. 1 the figure illustrates a cross-section of a portion of a semiconductor device 10 called an integrated circuit die.
• the semiconductor device 10 includes a substrate 12 having an NVM area 18 and a logic area 20 separated by a trench isolation 13.
• FIG. 1 shows a dielectric layer 14 and a first layer of gate material 16 overlying the substrate 12.
• the substrate 12 can be any semiconductor material or combination of materials, such as gallium arsenide, silicon, germanium, silicon-on-insulator (SOI), monocrystalline silicon or any other material that is conventionally used to form electronic devices.
• the trench isolation 13 is formed on the semiconductor device 10.
• the trench isolation 13 is required to electrically separate a first defined area and a second defined area on the semiconductor device 10.
• the first defined area includes the NVM area 18, which is used for implementing non-volatile memory cells and the second defined area includes the logic area 20, which is used for implementing transistors that implement logic functions.
• the NVM area 18 is electrically isolated from the logic area 20 by the trench isolation 13 corresponding to a minimum photolithography limit.
• the trench isolation 13 can be any oxide, often referred to as trench oxide.
• the dielectric layer 14 is then deposited over the substrate 12.
• the dielectric layer 14 can be an oxide such as silicon oxide, aluminium oxide, tantalum oxide, a nitride such as silicon nitride, titanium dioxide, and zirconium dioxide, the like and any combination thereof.
• the dielectric layer 14 can be deposited using conventional chemical vapor deposition (CVD) techniques, physical vapor deposition techniques, an atomic layer deposition technique, or a combination thereof.
• the dielectric layer 14 can include one or more films of silicon dioxide, silicon nitride, silicon oxynitride, a high-k material (e.g. k greater than 7), or any combination thereof.
• the first layer of gate material 16 is then deposited over the dielectric layer
• the first layer of gate material 16 can be any material, such as, polysilicon, amorphous Silicon (Si), Germanium (Ge), or SiGe, the like, or any combination thereof.
• the first layer of gate material 16 can be deposited using a conventional chemical vapor deposition technique, or may be deposited by other processes.
• the first layer of gate material 16 acts as select gate for the memory transistor in the NVM area 18.
• the first layer of gate material 16 also acts as a gate electrode for logic transistor in the logic area 20.
• deposition of the multiple adjoining sacrificial layers over the first layer of gate material 16 includes deposition of an anti-reflective coating (ARC) layer 22, an etch stop layer 24, and a polishing stop layer 26 one above another.
• the ARC layer 22 is formed over the first layer of gate material 16.
• the ARC layer 22 is a nitride (e.g., TiN), a metal-silicon nitride (e.g., Ta a Si b N c ), such as silicon nitride, a metal-containing nitride, or any combination thereof.
• the ARC layer 22 is deposited using a conventional chemical vapor deposition (CVD) technique having a thickness of approximately 155 A.
• the ARC layer 22 is used as an anti- reflective coating for patterning gate of a transistor in the logic area 20.
• the etch stop layer 24 is formed.
• the etch stop layer 24, can be an oxide such as, SiO 2, and the like.
• the etch stop layer 24 is an ultra-dense oxide layer (UDOX) having a thickness of 80 A.
• UEOX ultra-dense oxide layer
• the etch stop layer 24 is used to separate the ARC layer 22 from the polishing stop layer 26.
• the etch stop layer 24 is used to stop etching the polishing stop layer 26 in the etching process.
• the etch stop layer 24 prevents exposure of the ARC layer 22 from various processes performed during fabrication.
• the ARC layer 22 will be used to pattern the gate electrode of a logic transistor in the logic area 20.
• the polishing stop layer 26 is deposited using CVD having a thickness of approximately five times the thickness of the etch stop layer 24.
• the polishing stop layer 26 can be any nitride or oxynitride, such as, SiN, SiON, and the like.
• the polishing stop layer 26 is used to stop polishing in chemical mechanical polishing (CMP) process.
• CMP chemical mechanical polishing
• the polishing stop layer is used as an anti-reflective coating to pattern the select gate for the memory transistor in the NVM area 18.
• the ARC layer 22 contains nitrogen
• the etch stop layer 24 contains oxygen
• the polishing stop layer 26 contains nitrogen
• FIG. 3 depicts a patterned photoresist layer 28 consisting of a photoresist material deposited over the polishing stop layer 26.
• the patterned photoresist layer 28 is deposited using a conventional lithographic technique, for example, a spin-coating technique.
• the photoresist material can include a variety of photoresist chemicals suitable for lithographic applications.
• the photoresist material conventionally includes a matrix material or resin, a sensitizer or inhibitor, and a solvent.
• the material of the patterned photoresist layer 28 can be a positive photoresist material or a negative photoresist material.
• etching is performed using the patterned photoresist layer 28 as a mask.
• the etching is done to etch through the polishing stop layer 26, the etch stop layer 24, the ARC layer 22, and the first layer of gate material 16.
• the etching is performed using a dry etch technique.
• the patterned photoresist layer 28 is removed following the etching process.
• the photoresist is removed using conventional wet cleaning processes, such as, an RCA clean, a piranha clean, and the like.
• the photoresist is removed by using conventional stripping processes, such as, ashing, solvent cleaning, and the like.
• the exposed areas of the dielectric layer 14 are etched and a charge storage stack 30 is deposited over the patterned semiconductor device 10.
• the charge storage stack 30 is one layer or more than one layer of charge storage material.
• the charge storage stack 30 is deposited using conventional deposition techniques, for example, CVD, Plasma-enhanced CVD (PECVD), Low-pressure CVD (LPCVD), and the like.
• the charge storage stack 30 is a layer of nanocrystals, sandwiched between oxides.
• the charge storage stack 30 is a nitride sandwiched between oxides.
• the charge storage stack 30 is a layer of polysilicon, followed by an oxide-nitride-oxide (ONO) layer.
• the charge storage stack 30 is a layer of nanocrystals sandwiched between oxides.
• a polysilicon layer is deposited which acts as a floating gate for the patterned memory transistor of the NVM area 18.
• a second layer of gate material 32 is deposited over the
• the second layer of gate material 32 is deposited to fill the exposed area over the charge storage stack 30 and covers the charge storage stack 30 with a thick layer.
• the second layer of gate material 32 can be a metal, a polysilicon, or any combination of the two.
• the second layer of gate material 32 is deposited using a conventional method, such as, low pressure chemical vapor deposition (LPCVD), plasma- enhanced chemical vapor deposition (PECVD) and the like.
• FIG. 7 shows the semiconductor device 10 after polishing of the second layer of gate material 32.
• the polishing is done to remove the second layer of gate material 32, and the charge storage stack 30 overlying the polishing stop layer 26.
• the second layer of gate material 32 is polished using conventional techniques, such as, chemical mechanical polishing (CMP).
• CMP chemical mechanical polishing
• the second layer of gate material 32 is etched until the polishing stop layer 26 is exposed, by using the conventional etching processes.
• a photoresist mask 34 composed of a photoresist material is deposited.
• the second layer of gate material 32 is then removed from the exposed area.
• the second layer of gate material 32 is removed by using a selective dry etch process, such as, non-isotropic dry etch.
• FIG. 9 illustrates a photoresist mask 36 composed of a photoresist material deposited over the semiconductor device 10 of FIG. 8.
• the exposed area is then etched using the dry etch process.
• the exposed polishing stop layer 26, the etch stop layer 24, the ARC layer 22, and the first layer of gate material 16 are removed from the semiconductor device 10 of FIG. 8.
• the polishing stop layer 26 of the semiconductor device of FIG. 9 is selectively etched using a conventional dry etch process, such as, a non- isotropic technique.
• the dry etching is done in such a way that the second layer of gate material 32 remains unaffected and the polishing stop layer 26 is etched away.
• a wet etching process is performed on the semiconductor device 10 of FIG. 10.
• the wet etching process is a conventional wet etching process, such as, hydrofluoric (HF) etching.
• Other acids that can be used for a wet etching process include, but are not limited to, H 3 PO 4 , H 2 SO 4 , KOH, H 2 O 2 , and HCI.
• the wet etching process leads to removal of the etch stop layer 24, the exposed areas of charge storage stack 30 and the exposed dielectric layer 14.
• the formation of the select gate and the control gate in the NVM area 18 is complete.
• FIG. 12 illustrates a photoresist mask 38 composed of a photoresist material deposited for patterning the gate of logic transistor in the logic area 20.
• the gate of the logic transistor is patterned using the ARC layer 22.
• the exposed ARC layer 22 and the first layer of gate material 16 are removed from logic area 20 of the semiconductor device 10 of FIG. 11 using a dry etch process.
• the patterning avoids the need to deposit a BARC layer over a gate oxide to pattern the gate of logic transistor.
• the trench isolation 13 is made large to reduce the non-planarity problem while depositing BARC. Because the trench isolation 13 between the NVM area 18 and the logic area 20 can be associated with a minimum photolithographic limit, a significant amount of space can be saved on the integrated circuit.
• a set of spacers 40, 42 is respectively formed around the first layer of gate material 16 and the second layer of gate material 32 in the NVM area 18, and around the first layer of gate material 16 in the logic area 20.
• the set of spacers 40, 42 can be formed by depositing an insulating layer, such as, an oxide, a nitride, an oxynitride and the like, over the substrate and etching portions of the insulating layer.
• a source 44 and a drain 46 for the memory transistor 52 are formed in the NVM area 18.
• a source 48 and a drain 50 for the logic transistor 54 are formed in the logic area 20.
• the source 44, 48 and drain 46, 50 are respectively formed by conventional doping process.
• a memory transistor 52 is formed, and in the logic area 20, a logic transistor 54 is formed.
• the first layer of gate material 16 acts as a select gate and the second layer of gate material 32 acts as a control gate for the memory transistor 52 in the NVM area 18.
• the first layer of gate material 16 also acts as a gate for the logic transistor 54 in the logic area 20.
• NVM area, first defined area and first region represent the memory region and the terms logic area, second defined area and second region represents the logic region in the semiconductor device 10.
• first layer of gate material and first gate electrode material represents the select gate in the NVM area 18 as well as the gate electrode in the logic area 20.
• second layer of gate material and second gate electrode material represent the control gate in the NVM area 18.
• first type of device and “memory transistor” represent a transistor in the memory area and the terms “second type of device” and “logic transistor” represents a transistor used for performing logic functions in the logic area.
• the structures described herein utilize multiple sacrificial layers containing a stack of nitride, oxide, and nitride (ARC layer) to pattern the select gate of a memory transistor in a memory circuit area and a gate electrode of a logic transistor in a logic circuit area.
• ARC layer nitride, oxide, and nitride
• process complexities in integration of NVM and logic devices are reduced significantly.
• the present invention uses the ARC layer from the Nitride/Oxide/Nitride stack for this purpose. Due to this, the size of the trench isolation area need not be large which leads to optimal space utilization in the SoC. Further, the present invention enables seamless integration of NVM memories into SoC.
• a method for integrating NVM circuitry with logic circuitry by providing a substrate having a first defined area and a second defined area that is electrically separated from first defined area.
• a first layer of gate material is provided overlying the substrate in both the first defined area and the second defined area.
• Multiple adjoining sacrificial layers overlying the first layer of gate material are provided.
• the multiple adjoining sacrificial layers are provided to form transistor control electrodes in the first defined area wherein at least one of the adjoining sacrificial layers is not completely removed. At least one of the adjoining sacrificial layers is used to pattern transistor control electrode in the second defined area. Formation of transistors in both the first defined area and the second defined area is completed.
• the at least one of the adjoining sacrificial layers is immediately adjacent the transistor control electrode in the second defined area.
• the multiple adjoining sacrificial layers further include a first nitride layer overlying an oxide layer that overlies a second nitride layer.
• the first defined area includes a non-volatile memory area for implementing non-volatile memory cells and the second defined area includes a logic area for implementing transistors that implement logic functions.
• the first defined area is electrically isolated from the second defined area by an amount corresponding to a minimum photolithography limit.
• At least one of the multiple adjoining sacrificial layers includes a polishing stop layer for use in chemical mechanical polishing, at least one of the multiple adjoining sacrificial layers includes an etch stop layer for use in chemical etching, and at least one of the multiple adjoining sacrificial layers includes an anti-reflective coating (ARC) layer.
• the multiple adjoining sacrificial layers are completely removed at completion of processing of the first defined area and the second defined area.
• the multiple adjoining sacrificial layers include an anti-reflective coating (ARC) layer overlying the substrate, an oxide layer overlying the anti-reflective coating layer, and a nitride layer overlying the oxide layer.
• a method of forming an integrated circuit including a first region and a second region formed over a substrate and separated by an isolation region.
• a first gate electrode material layer is formed overlying the substrate in both the first region and the second region.
• a plurality of sacrificial layers is formed overlying the first gate electrode material layer in both the first region and the second region prior to forming any devices in the first region and the second region.
• the plurality of sacrificial layers is used to form a first type of device in the first region. At least one of the plurality of sacrificial layers is used to form a second type of device in the second region.
• the plurality of sacrificial layers is removed from the first region prior to forming gate electrodes corresponding to the second type of device in the second region.
• the at least one of the plurality of sacrificial layers is used to form the second type of device immediately adjacent to the first gate electrode material layer.
• the at least one of the plurality of sacrificial layers used to form the second type of device is an anti-reflective coating (ARC) layer.
• ARC anti-reflective coating
• the plurality of sacrificial layers includes an anti- reflective coating (ARC) layer used to pattern a gate electrode corresponding to the second type of device formed in the second region, a polishing stop layer used to stop polishing of a polysilicon layer formed in both the first region and the second region, and an etch stop layer used to stop etching the polishing stop layer in both the first region and the second region.
• ARC anti- reflective coating
• the first region is a memory region and the second region is a logic region.
• the first type of device includes a control gate and a select gate, and the second type of device includes only one gate.
• a method of forming an integrated circuit including a memory region and a logic region formed over a substrate and separated by an isolation region.
• a first gate electrode material layer is formed overlying the substrate in both the memory region and the logic region.
• a plurality of sacrificial layers is formed overlying the first gate electrode material layer in both the memory region and the logic region prior to forming any devices in the memory region and the logic region. The plurality of sacrificial layers is used to form a non-volatile memory device in the memory region.
• At least one of the plurality of sacrificial layers is used to form a logic device in the logic region, wherein the at least one of the plurality of sacrificial layers used to form the logic device is an anti- reflective coating (ARC) layer used to pattern a gate electrode corresponding to the logic region.
• ARC anti- reflective coating
• the plurality of sacrificial layers is removed from the memory region prior to forming the gate electrode corresponding to the logic device in the logic region.
• the at least one of the plurality of sacrificial layers that is used to form the logic device is immediately adjacent to the first gate electrode material layer.
• the plurality of sacrificial layers includes a polishing stop layer used to stop polishing of a polysilicon layer formed in both the memory region and the logic region, an etch stop layer used to stop etching the polishing stop layer in both the memory region and the logic region.
• the ARC layer contains nitrogen
• the polishing stop layer contains nitrogen
• the etch stop layer contains oxygen.

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• 2007
  • 2007-10-29 US US11/926,348 patent/US7745344B2/en active Active
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