CN101842899B - 将nvm电路与逻辑电路集成的方法 - Google Patents
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Abstract
提供一种用于使非易失性存储器(NVM)电路(18)与逻辑电路(20)集成的方法。该方法包括沉积将第一栅极材料层(16)沉积于基板(12)的NVM区域和逻辑区域之上。该方法还包括沉积包含相互覆盖的氮化物、氧化物及氮化物(ARC层)的多个邻接牺牲层(22、24、26)。使用多个邻接牺牲层(22、24、26)来图形化NVM区域中的存储器晶体管的选择栅极(16)及控制栅极(32),而使用多个邻接牺牲层(22、24、26)的ARC层(22)来图形化逻辑区域(20)中的逻辑晶体管的栅极(16)。
Description
技术领域
本发明一般地涉及集成电路制造,并且更具体地,涉及在制作集成电路设计中将非易失性存储器(NVM)电路与逻辑电路集成。
背景技术
在集成电路设计领域中,通常使用片上系统(SoC)器件。术语“SoC”指的是将几种类型的模块集成于单个集成电路上的器件,这些类型的模块包括逻辑、可编程部件、I/O、易失性存储器及非易失性存储器。
在SoC设计中常常将基于浮栅的存储器用作非易失性存储器。为了克服在SoC上所嵌入的基于浮栅的存储器的尺度限制,目前正使用薄膜存储(TFS)的存储器。在TFS存储器中,电荷被存储于包含硅晶体(通常称为纳米晶体)的薄的绝缘膜中。
TFS(薄膜存储)存储器与逻辑电路在SoC中的集成需要两种栅极蚀刻,一种用于TFS区域中的选择栅极而另一种则用于逻辑区域中的逻辑或外围晶体管的栅极。逻辑或外围晶体管是很小的,具有临界尺寸,并且从而要图形化是复杂的。在一种途经中,使用沉积于栅极氧化物之上的底部抗反射涂料(BARC)层来图形化微小晶体管的栅极以实现对晶体管的栅极尺寸的临界尺寸(CD)的控制。由于BARC具有高粘度,因而难以沉积BARC层。此外,如果在SoC上的存储器区域与逻辑区域之间的高度有差别则过程变得更为复杂。另外,如果在SoC上的存储器区域与逻辑区域之间的物理距离小,则很厚的非平面BARC层沉积于逻辑区域中的栅极氧化物上,该BARC层难以蚀刻。另外,使用厚BARC层进行的晶体管栅极的图形化是复杂的过程,因为厚的BARC层也是抗反射的。要解决这种非平面性问题,需要存储器区域与逻辑区域之间的距离(被称作隔离区)是大的。但是,隔离区的增加会带来SoC设计中的布局效率低。
用于图形化小尺寸晶体管的另一种途经包括沉积规则的抗反射涂层(ARC)或氮化物。但是,由于非平面性问题因而要在之后的过程中蚀刻它是困难的。
需要在将集成NVM电路与逻辑电路集成于SoC中时克服这些问题并降低过程复杂性的方法。
附图说明
下面对本发明的优选实施方案的详细描述在结合附图来阅读时将会更好理解。本发明通过实例的方式来说明,但不限定于附图,在附图中相似的标记指示相似的元素。图中的元素出于简单清晰的目的来示出而并不一定按比例绘制。
图1示出了根据本发明的实施方案具有覆盖于基板之上的电介质材料层及栅极材料层的半导体器件的一部分的截面;
图2示出了根据本发明的实施方案在沉积了多个邻接的牺牲层之后的图1的半导体器件;
图3示出了根据本发明的实施方案在沉积了图形化的光致抗蚀剂层之后的图2的半导体器件;
图4示出了根据本发明的实施方案在蚀刻了牺牲层及第一栅极材料层之后的图3的半导体器件;
图5示出了根据本发明的实施方案的在将电荷存储叠层沉积于牺牲层上之后的图4的半导体器件;
图6示出了根据本发明的实施方案在沉积第二栅极材料层之后的图5的半导体器件;
图7示出了根据本发明的实施方案在抛光穿过第二栅极材料层到抛光终止层之后的图6的半导体器件;
图8-11示出了根据本发明的实施方案的选择栅极及控制栅极在图7的半导体器件的NVM区域中的形成。
图12示出了根据本发明的实施方案在为了图形化逻辑区域中的逻辑晶体管的栅极而沉积光致抗蚀剂掩模之后的图11的半导体器件;以及
图13示出了根据本发明的实施方案用于在存储器区域中形成存储器晶体管以及在逻辑区域中形成逻辑晶体管的最后处理步骤。
本领域技术人员将会意识到图中的元素出于简单清晰的目的来说明而并不一定按比例绘制。例如,图中的某些元件的尺寸可以相对其他元件放大以帮助提高对本发明的实施方案的理解。
具体实施方式
对附图的详细描述是要描述本发明当前优选的实施方案,而并不是要表示可以实施本发明的唯一形式。应当理解,相同的或相当的功能可以通过确定包含于本发明的精神及范围之内的不同实施方案来完成。
在本发明的实施方案中,方法提供了具有相互电隔离的第一界定区域以及第二界定区域的基板。另外,该方法在第一界定区域及第二界定区域两者中提供了覆盖于基板上的第一栅极材料层。此外,该方法提供了覆盖于第一栅极材料层上的多个邻接牺牲层。该方法还使用了多个邻接牺牲层来在第一界定区域中形成晶体管控制电极,在该第一界定区域中至少一层邻接牺牲层没有被完全去除。另外,该方法使用邻接牺牲层中的一个来在第二界定区域中图形化晶体管控制电极。最后,该方法在第一界定区域及第二界定区域两者中完成晶体管的形成。
在本发明的另一种实施方案中,提供了形成集成电路的方法。集成电路包括形成于基板上的并且由隔离区所隔开的第一区及第二区。该方法包括在第一区和第二区二者中形成覆盖于基板之上的第一栅电极材料层。此外,该方法在将任意器件形成于第一区和第二区二者中之前在第一区和第二区中形成覆盖于第一栅电极材料层之上的多个牺牲层。另外,该方法包括使用该多个牺牲层来在第一区中形成第一类器件。而且,该方法包括使用该多个牺牲层来在第二区中形成第二类器件。
在又一种实施方案中提供了形成集成电路的方法。集成电路包括形成于基板上并由隔离区隔开的存储器区和逻辑区。该方法包括在存储器区和逻辑区二者中形成覆盖于基板之上的第一栅电极材料层。该方法还包括在将任意器件形成于存储器区和逻辑区二者中之前在存储器区和逻辑区中形成覆盖于第一栅电极材料层之上的多个牺牲层。另外,该方法包括使用该多个牺牲层来在存储器区中形成非易失性存储器件。并且,该方法包括使用该多个牺牲层中的至少一层来在逻辑区中形成逻辑器件。该多个牺牲层中用来形成逻辑器件的至少一层牺牲层是用来图形化与逻辑区中的逻辑器件对应的栅电极的抗反射涂料(ARC)层。
图1-13示出了根据本发明的各种实施方案在将非易失性存储器(NVM)电路与逻辑电路集成的阶段期间的半导体晶片的一部分的截面。
现在参考图1,该图示出了半导体器件10(称为集成电路管芯)的一部分的截面。半导体器件10包括具有由沟槽隔离13所隔开的NVM区域18和逻辑区域20的基板12。图1示出了覆盖于基板12之上的电介质层14及第一栅极材料层16。基板12可以是任意半导体材料或者材料组合,例如砷化镓、硅、锗、绝缘体上硅(SOI)、单晶硅或者通常用来形成电子器件的其他任意材料。如图1所示,在半导体器件10上形成了沟槽隔离13。需要沟槽隔离13来对半导体器件10上的第一界定区域及第二界定区域进行电隔离。第一界定区域包括用于实现非易失性存储器单元的NVM区域18而第二界定区域包括用于实现执行逻辑功能的晶体管的逻辑区域20。在本发明的一种实施方案中,NVM区域18通过与最小光刻限度对应的沟槽隔离13与逻辑区域20进行电隔离。沟槽隔离13可以是通常称作沟槽氧化物的任意氧化物。
然后,电介质层14被沉积于基板12之上。电介质层14可以是氧化物(例如氧化硅、氧化铝、氧化钽)、氮化物(例如氮化硅)、二氧化钛、及二氧化锆等以及它们的任意组合。电介质层14可以使用常规的化学汽相沉积(CVD)技术、物理汽相沉积技术、原子层沉积技术、或它们的组合来沉积。电介质层14可以包括一层或更多层二氧化硅膜、氮化硅膜、氧氮化硅膜、高k值材料(例如k大于7)膜,或者它们的任意组合。
然后将第一栅极材料层16沉积于电介质层14之上。第一栅极材料层16可以是任意材料,例如,多晶硅、非晶硅(Si)、锗(Ge)、或SiGe等,或者它们的任意组合。第一栅极材料层16可以使用常规的汽相沉积技术来沉积,或者可以通过其他过程来沉积。
在一种实施方案中,在所有处理步骤完成并且晶体管在NVM区域18及逻辑区域20中形成之后,第一栅极材料层16充当用于NVM区域18中的存储器晶体管的选择栅极。第一栅极材料层16还充当用于逻辑区域20中的逻辑晶体管的栅电极。
现在参考图2,多个平面的邻接的牺牲层在第一栅极材料层16之上的沉积包括一层叠一层地沉积抗反射涂料(ARC)层22、蚀刻终止层24、及抛光终止层26。ARC层22被形成于第一栅极材料层16之上。在优选的实施方案中,ARC层22是氮化物(如,TiN)、金属-硅氮化物(如,TaaSibNc),例如氮化硅、含金属氮化物,或者它们的任意组合。在优选的实施方案中,使用常规的化学汽相沉积(CVD)技术来沉积厚度为大约的ARC层22。ARC层22被用作用于图形化逻辑区域20中的晶体管的栅极的抗反射涂层。
在沉积了ARC层22之后,形成蚀刻终止层24。蚀刻终止层24可以是氧化物,例如SiO2等。在一种实施方案中,蚀刻终止层24是厚度为的超密氧化物层(UDOX)。使用蚀刻终止层24来分隔ARC层22与抛光终止层26。使用蚀刻终止层24来在蚀刻过程中终止对抛光终止层26的蚀刻。因而,蚀刻终止层24防止ARC层22在制造期间暴露于所执行的各种过程。将使用ARC层22来图形化逻辑区域20中的逻辑晶体管的栅电极。
在一种形式中,使用CVD来沉积厚度为蚀刻终止层24厚度的大约5倍的抛光终止层26。抛光终止层26可以是任意氮化物或氧氮化物,例如,SiN、SiON等。使用抛光终止层26来在化学机械抛光(CMP)过程中终止抛光。在本发明中,抛光终止层被用作抗反射涂层以图形化NVM区域18中的存储器晶体管的选择栅极。
在一种形式中,ARC层22含有氮,蚀刻终止层24含有氧,而抛光终止层26含有氮。
图3示出了包含沉积于抛光终止层26之上的光致抗蚀剂材料的图形化的光致抗蚀剂层28。图形化的光致抗蚀剂层28使用常规的光刻技术(例如,旋涂技术)来沉积。光致抗蚀剂材料可以包括适合于光刻应用的多种光致抗蚀剂化学品。光致抗蚀剂材料通常包括基体材料(matrix material)或树脂,感光剂或抑制剂,以及溶剂。图形化的光致抗蚀剂层28的材料可以是正性光致抗蚀剂材料或负性光致抗蚀剂材料。
如图4所示,将图形化的光致抗蚀剂层28用作掩模来执行蚀刻。进行该蚀刻以蚀刻穿过抛光终止层26、蚀刻终止层24、ARC层22、及第一栅极材料层16。在一种实施方案中,使用干法蚀刻技术来执行蚀刻。图形化的光致抗蚀剂层28在蚀刻过程之后被去除。在一种实施方案中,光致抗蚀剂使用常规的湿法清洗过程来去除,例如,RCA清洗、过氧硫酸(piranha)清洗等。在另一种实施方案中,光致抗蚀剂使用常规的条纹化过程来去除,例如,灰化、溶剂清洗等。
如图5所示,电介质层14的露出区域被蚀刻并且电荷存储叠层30被沉积于图形化的半导体器件10之上。电荷存储叠层30是一层或者多于一层的电荷存储材料。在一种实施方案中,电荷存储叠层30使用常规的沉积技术来沉积,例如,CVD、等离子体增强CVD(PECVD)、低压CVD(LPCVD)等。在一种实施方案中,电荷存储叠层30是夹在氧化物之间的纳米晶体层。在另一种实施方案中,电荷存储叠层30是夹在氧化物之间的氮化物。在又一种实施方案中,电荷存储叠层30是继之以氧化物-氮化物-氧化物(ONO)层的多晶硅层。在优选的实施方案中,电荷存储叠层30是夹在氧化物之间的纳米晶体层。
在本发明的实施方案中,在图形化的半导体器件10上不是沉积电荷存储叠层30,而是沉积充当用于NVM区域18的图形化存储器晶体管的浮栅的多晶硅层。
参考图6,第二栅极材料层32被沉积于NVM区域18及逻辑区域20之上。第二栅极材料层32被沉积以填充电荷存储叠层30之上的露出区域并且用厚层来覆盖电荷存储叠层30。第二栅极材料层32可以是金属、多晶硅,或该二者的任意组合。第二栅极材料层32使用常规的方法来沉积,例如,低压化学汽相沉积(LPCVD)、等离子体增强化学汽相沉积(PECVD)等。
图7示出了在对第二栅极材料层32进行抛光之后的半导体器件10。进行该抛光以去除第二栅极材料层32,以及覆盖于抛光终止层26之上的电荷存储叠层30。第二栅极材料层32使用常规的技术来抛光,例如,化学机械抛光(CMP)。在一种实施方案中,使用常规的蚀刻过程来蚀刻第二栅极材料层32直到抛光终止层26露出。
按照图8,包括光致抗蚀剂材料的光致抗蚀剂掩模34被沉积。然后将第二栅极材料层32从露出区域中去除。在一种实施方案中,使用选择性干法蚀刻过程来去除第二栅极材料层32,例如,各向异性的干法蚀刻。
图9示出了沉积于图8的半导体器件10之上的包括光致抗蚀剂材料的光致抗蚀剂掩模36。然后使用干法蚀刻过程来蚀刻露出区域。在该过程中,将露出的抛光终止层26、蚀刻终止层24、ARC层22、及第一栅极材料层16从图8的半导体器件10中去除。
如图10所示,对图9的半导体器件的抛光终止层26使用常规的干法蚀刻过程(例如,各向异性技术)来进行选择性蚀刻。该干法蚀刻通过使第二栅极材料层32保持不受影响并将抛光终止层26蚀刻掉的方式来进行。
如图11所示,在图10的半导体器件10上执行湿法蚀刻过程。在一种形式中,该湿法蚀刻过程是常规的湿法蚀刻过程,例如,氢氟酸(HF)蚀刻。其他能够用于湿法蚀刻过程的酸包括,但不限于,H3PO4、H2SO4、KOH、H2O2、及HCl。湿法蚀刻过程会导致蚀刻终止层24、电荷存储叠层30的露出区域及露出的电介质层14的去除。因而,在湿法蚀刻过程完成时,NVM区域18中的选择栅极及控制栅极的形成就完成。
图12示出了为了图形化逻辑区域20中的逻辑晶体管的栅极而沉积的包括光致抗蚀剂材料的光致抗蚀剂掩模38。在此,使用ARC层22来图形化逻辑晶体管的栅极。使用干法蚀刻过程将露出的ARC层22及第一栅极材料层16从图11的半导体器件10的逻辑区域20中去除。
由于使用ARC层22来图形化逻辑晶体管的栅极,因而该图形化不需要在栅极氧化物之上沉积BARC层来图形化逻辑晶体管的栅极。而且,在沉积BARC的情况下,必须使沟槽隔离13变成大的以减小非平面性问题。因为在NVM区域18与逻辑区域20之间的沟槽隔离13能够与最小的光刻限度相关联,所以能够在集成电路上节省相当数量的空间。
现在参考图13,将光致抗蚀剂掩模38及ARC层22从图12的半导体器件10中去除。一组间隔物40、42分别被形成于NVM区域18中的第一栅极材料层16及第二栅极材料层32周围,以及在逻辑区域20中的第一栅极材料层16周围。该组间隔物40、42能够通过将绝缘层(例如,氧化物、氮化物、氧氮化物等)沉积于基板之上并蚀刻该绝缘层的一部分来形成。存储器晶体管52的源极44和漏极46被形成于NVM区域18中。逻辑晶体管54的源极48和漏极50被形成于逻辑区域20中。源极44、48和漏极46、50分别通过常规的掺杂过程来形成。因而,存储器晶体管52形成于NVM区域18中而逻辑晶体管54则形成于逻辑区域20中。第一栅极材料层16充当选择栅极而第二栅极材料层32则充当NVM区域18中的存储器晶体管52的控制栅极。第一栅极材料层16还充当逻辑区域20中的逻辑晶体管54的栅极。
如在此所使用的,术语NVM区域、第一界定区域及第一区表示存储器区而术语逻辑区域、第二界定区域及第二区则表示半导体器件10中的逻辑区。
如在此所使用的,术语“第一栅极材料层”和“第一栅电极材料”表示NVM区域18中的选择栅极以及逻辑区域20中的栅电极。术语“第二栅极材料层”和“第二栅电极材料”表示NVM区域18中的控制栅极,该控制栅极与选择栅极横向相邻,如图7-13所示。
如在此所使用的,术语“第一类器件”和“存储器晶体管”表示存储器区域中的晶体管而术语“第二类器件”和“逻辑晶体管”则表示用于执行逻辑区域中的逻辑功能的晶体管。
在此所描述的结构利用含有氮化物、氧化物、及氮化物(ARC层)的叠层的多个牺牲层来图形化存储器电路区域中的存储器晶体管的选择栅极以及逻辑电路区域中的逻辑晶体管的栅电极。因而,显著降低了在NVM器件与逻辑器件的集成中的过程复杂性。取代使用BARC层来图形化逻辑区域中的栅电极,本发明对于该目的使用了氮化物/氧化物/氮化物叠层的ARC层。由于这个原因,沟槽隔离区域的尺寸不需要是大的,这导致了SoC中最优的空间利用。此外,本发明使NVM存储器能够无缝地集成于SoC中。
在一种形式中,在此提供了用于通过提供具有第一界定区域以及与第一界定区域电隔离的第二界定区域的基板来使NVM电路与逻辑电路集成的方法。在第一界定区域及第二界定区域二者中提供覆盖于基板之上的第一栅极材料层。提供覆盖于第一栅极材料层之上的多个邻接牺牲层。提供多个邻接牺牲层以在第一界定区域中形成晶体管控制电极,其中邻接牺牲层中的至少一层没有被完全去除。使用邻接牺牲层中的至少一层来图形化第二界定区域中的晶体管控制电极。在第一界定区域和第二界定区域中的晶体管的形成得以完成。
在另一种形式中,所述邻接牺牲层中的至少一层与第二界定区域中的晶体管控制电极直接邻接。在另一种形式中,该多个邻接牺牲层还包括覆盖于氧化物层之上的第一氮化物层,其中该氧化物层覆盖于第二氮化物层之上。在另一种形式中,第一界定区域包括用于实现非易失性存储器单元的非易失性存储器区域而第二界定区域包括用于实现执行逻辑功能的晶体管的逻辑区域。在又一种形式中,第一界定区域与第二界定区域电隔开对应于最小光刻限度的量。在又一种形式中,多个邻接牺牲层中的至少一层包括在化学机械抛光中使用的抛光终止层,多个邻接牺牲层中的至少一层包括在化学蚀刻中使用的蚀刻终止层,以及多个邻接牺牲层中的至少一层包括抗反射涂料(ARC)层。在又一种形式中,多个邻接牺牲层在对第一界定区域及第二界定区域处理完成时被完全去除。在一种形式中,多个邻接牺牲层包括覆盖于基板之上的抗反射涂料(ARC)层,覆盖于抗反射涂料层之上的氧化物层,以及覆盖于氧化物层之上的氮化物层。
在另一种形式中,在此提供了方法,形成包括形成于基板之上并由隔离区所隔开的第一区和第二区的集成电路。在第一区和第二区二者中形成覆盖于基板之上的第一栅电极材料层。在将任意器件形成于第一区和第二区二者中之前于第一区和第二区中形成覆盖于第一栅电极材料层之上的多个牺牲层。使用多个牺牲层来在第一区中形成第一类器件。使用多个牺牲层中的至少一层来在第二区中形成第二类器件。
在另一种形式中,在形成与第二区中的第二类器件对应的栅电极之前将多个牺牲层从第一区中去除。在另一种形式中,使用多个牺牲层中的至少一层来形成直接邻接于第一栅电极材料层的第二类器件。在又一种形式中,用来形成第二类器件的多个牺牲层中的至少一层是抗反射涂料(ARC)层。在另一种形式中,用来图形化与第二类器件对应的栅电极的ARC层被形成于第二区中。在又一种形式中,多个牺牲层包括用来图形化与在第二区中所形成的第二类器件对应的栅电极的抗反射涂料(ARC)层,用来终止对在第一区和第二区二者中所形成的多晶硅层的抛光的抛光终止层,以及用来终止对在第一区和第二区中的抛光终止层的蚀刻的蚀刻终止层。在又一种形式中,第一区域是存储器区而第二区是逻辑区。在另一种形式中,第一类器件包括控制栅极和选择栅极,而第二类器件只包括一种栅极。
在又一种形式中,提供了用于形成包括在基板上所形成的并由隔离区所隔开的存储器区及逻辑区的集成电路的方法。在存储器区和逻辑区二者中形成覆盖于基板之上的第一栅电极材料层。在将任意器件形成于存储器区和逻辑区二者中之前于存储器区和逻辑区中形成覆盖于第一栅电极材料层之上的多个牺牲层。使用多个牺牲层来在存储器区中形成非易失性存储器件。使用多个牺牲层中的至少一层来在逻辑区中形成逻辑器件,其中用来形成逻辑器件的多个牺牲层中的至少一层是用来图形化对应于逻辑区的栅电极的抗反射涂料(ARC)层。在另一种形式中,在形成与逻辑区的逻辑器件对应的栅电极之前将多个牺牲层从存储器区中去除。在另一种形式中,用来形成逻辑器件的多个牺牲层中的至少一层直接邻接于第一栅电极材料层。在另一种形式中,多个牺牲层包括用来终止对在存储器区和逻辑区二者中形成的多晶硅层的抛光的抛光终止层,用来终止对存储器区和逻辑区二者中的抛光终止层的蚀刻的蚀刻终止层。在又一种形式中,ARC层含有氮,抛光终止层含有氮,而蚀刻终止层含有氧。
应当注意,并非在以上的一般描述或实例中描述的所有动作都需要,部分具体动作可以不需要,并且除了所描述的动作之外还可以执行一种或更多种动作。而且,动作所列出的次序并不一定是动作所执行的次序。
任意一种或更多种益处,一种或更多种其他优势,一个或更多个问题的一种或更多种解决方案,或者它们的任意组合在上文已经针对一种或更多种具体实施方案进行了描述。但是,益处、优势、问题的解决方案,或者可以促使任意优势、优势、或解决方案出现或变得更明显的的任意元素并不应被看作任意或所有权利要求的关键的、必需的、或者本质的特征或元素。
以上所公开的主题内容应被看作是示意性的,而非限制性的,并且所附权利要求意指涵盖属于本发明的范围内的所有修改、改进、及其他实施方案。因而,在法律允许的最大限度上,本发明的范围应当由下列权利要求的最广泛允许的解释及其等同物来确定,而不应当由以上详细描述所限制或限定。
Claims (10)
1.一种形成半导体器件的方法,包括:
提供具有第一界定区域以及与所述第一界定区域电隔离的第二界定区域的基板,所述第一界定区域用于形成非易失性存储器单元,所述非易失性存储器单元具有与控制栅极横向相邻的选择栅极,所述第二界定区域用于形成具有栅电极的晶体管;
在所述第一界定区域和所述第二界定区域二者中提供覆盖于所述基板之上的第一栅极材料层;
在所述第一界定区域和所述第二界定区域二者中提供覆盖于所述第一栅极材料层之上的多个邻接平面牺牲层,并且所述多个邻接平面牺牲层分别包含覆盖的氮、氧和氮;
使用所述多个邻接平面牺牲层来在所述第一界定区域中形成所述选择栅极和所述控制栅极,其中所述多个邻接平面牺牲层中的位于氧下方的氮没有被完全去除,而氧和覆盖的氮被去除;
在形成所述选择栅极和控制栅极之后,使用所述邻接平面牺牲层中的氮层来图形化在所述第二界定区域中的所述晶体管的栅电极;以及
完成在所述第一界定区域和所述第二界定区域二者中的晶体管形成。
2.根据权利要求1的方法,其中所述第一界定区域与所述第二界定区域电隔开与最小光刻限度对应的量。
3.根据权利要求1的方法,其中所述多个邻接平面牺牲层中的覆盖氧的氮用作在化学机械抛光中使用的抛光终止层,所述多个邻接平面牺牲层中的氧用作在化学蚀刻中使用的蚀刻终止层,并且所述多个邻接平面牺牲层中的位于氧下方的氮用作抗反射涂料层。
4.根据权利要求1的方法,其中所述多个邻接平面牺牲层在对所述第一界定区域及所述第二界定区域处理完成后被完全去除,并且所述方法还包括:
使位于氧下方的氮用作覆盖于所述基板之上的抗反射涂料层;
使氧用作覆盖于所述抗反射涂料层之上的氧化物层;以及
使覆盖氧的氮用作覆盖于所述氧化物层之上的氮化物层。
5.一种形成包括在基板上形成的并由隔离区所隔开的第一区和第二区的集成电路的方法,该方法包括:
在所述第一区和所述第二区二者中形成覆盖于所述基板之上的第一栅电极材料层;
在将任意器件形成于所述第一区和所述第二区中之前于所述第一区和所述第二区二者中形成覆盖于所述第一栅电极材料层之上的多个平面牺牲层,所述多个平面牺牲层分别包含覆盖的氮层、氧层和氮层;
使用所述多个平面牺牲层来在所述第一区中形成存储器单元,所述存储器单元具有与控制栅极横向相邻的选择栅极,其中所述平面牺牲层中的氧层和覆盖的氮层被去除;以及
在形成所述选择栅极和控制栅极之后,使用所述多个平面牺牲层中的位于氧下方的氮来在所述第二区中形成第二类器件的控制电极。
6.根据权利要求5的方法,其中位于氧下方的氮用作抗反射涂料层。
7.根据权利要求6的方法,其中位于氧下方的氮用作覆盖于所述基板之上的抗反射涂料层,氧用作覆盖于所述抗反射涂料层之上的氧化物层,并且覆盖氧的氮用作覆盖于所述氧化物层之上的氮化物层。
8.一种形成包括在基板上形成的并由隔离区所隔开的存储器区和逻辑区的集成电路的方法,该方法包括:
在所述存储器区和所述逻辑区二者中形成覆盖于所述基板之上的第一栅电极材料层;
在将任意器件形成于所述存储器区和所述逻辑区中之前于所述存储器区和所述逻辑区二者中形成覆盖于所述第一栅电极材料层之上的多个平面牺牲层,所述多个平面牺牲层分别包含覆盖的氮层、氧层和氮层;
使用所述多个平面牺牲层来在所述存储器区中形成非易失性存储器件,所述非易失性存储器单元具有与控制栅极横向相邻的选择栅极,其中所述多个平面牺牲层中的氧层和覆盖的氮层被去除;以及
使用所述多个平面牺牲层中的位于氧下方的氮来在所述逻辑区中形成逻辑器件,其中所述多个平面牺牲层中的位于氧下方的氮被用来形成所述逻辑器件的栅电极,并且用作用来图形化所述栅电极的抗反射涂料层。
9.根据权利要求8的方法,还包括在形成所述逻辑区中的所述逻辑器件的所述栅电极之前将所述多个平面牺牲层中的氧和覆盖氧的氮从所述存储器区中去除。
10.根据权利要求8的方法,其中氧用作覆盖于所述抗反射涂料层之上的氧化物层,并且覆盖氧的氮用作覆盖于所述氧化物层之上的氮化物层,氧和覆盖氧的氮在形成所述逻辑器件的所述栅电极之前被去除。
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- 2008-09-18 AT AT08844581T patent/ATE554501T1/de active
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- 2008-09-18 EP EP08844581A patent/EP2206151B1/en active Active
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WO2009058486A1 (en) | 2009-05-07 |
ATE554501T1 (de) | 2012-05-15 |
EP2206151A4 (en) | 2010-11-24 |
TWI437667B (zh) | 2014-05-11 |
EP2206151A1 (en) | 2010-07-14 |
CN101842899A (zh) | 2010-09-22 |
JP2011502353A (ja) | 2011-01-20 |
US7745344B2 (en) | 2010-06-29 |
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US20090111226A1 (en) | 2009-04-30 |
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