KR20090086148A - 리드 프레임 및 그것을 이용한 회로 장치의 제조 방법 - Google Patents

리드 프레임 및 그것을 이용한 회로 장치의 제조 방법 Download PDF

Info

Publication number
KR20090086148A
KR20090086148A KR1020080127219A KR20080127219A KR20090086148A KR 20090086148 A KR20090086148 A KR 20090086148A KR 1020080127219 A KR1020080127219 A KR 1020080127219A KR 20080127219 A KR20080127219 A KR 20080127219A KR 20090086148 A KR20090086148 A KR 20090086148A
Authority
KR
South Korea
Prior art keywords
lead frame
groove
unit
support portion
support
Prior art date
Application number
KR1020080127219A
Other languages
English (en)
Korean (ko)
Inventor
데쯔야 후꾸시마
다까시 기따자와
Original Assignee
산요덴키가부시키가이샤
산요 세미컨덕터 컴퍼니 리미티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 산요덴키가부시키가이샤, 산요 세미컨덕터 컴퍼니 리미티드 filed Critical 산요덴키가부시키가이샤
Publication of KR20090086148A publication Critical patent/KR20090086148A/ko

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
KR1020080127219A 2008-02-06 2008-12-15 리드 프레임 및 그것을 이용한 회로 장치의 제조 방법 KR20090086148A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2008025930A JP5144294B2 (ja) 2008-02-06 2008-02-06 リードフレームおよびそれを用いた回路装置の製造方法
JPJP-P-2008-025930 2008-02-06

Publications (1)

Publication Number Publication Date
KR20090086148A true KR20090086148A (ko) 2009-08-11

Family

ID=41071116

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020080127219A KR20090086148A (ko) 2008-02-06 2008-12-15 리드 프레임 및 그것을 이용한 회로 장치의 제조 방법

Country Status (3)

Country Link
JP (1) JP5144294B2 (fr)
KR (1) KR20090086148A (fr)
TW (1) TW200939439A (fr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5215980B2 (ja) * 2009-10-30 2013-06-19 株式会社三井ハイテック 半導体装置の製造方法
JP5397195B2 (ja) * 2009-12-02 2014-01-22 日立化成株式会社 光半導体素子搭載用基板の製造方法、及び、光半導体装置の製造方法
JP5613463B2 (ja) * 2010-06-03 2014-10-22 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法
DE102015100025A1 (de) 2015-01-05 2016-07-07 Osram Opto Semiconductors Gmbh Leiterrahmen
JP6924411B2 (ja) * 2017-08-28 2021-08-25 大日本印刷株式会社 リードフレームおよび半導体装置の製造方法
JP2022184057A (ja) * 2021-05-31 2022-12-13 Ｔｏｗａ株式会社 成形型、樹脂成形装置及び樹脂成形品の製造方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001077235A (ja) * 1999-09-06 2001-03-23 Mitsui High Tec Inc 半導体素子搭載用基板
JP3634757B2 (ja) * 2001-02-02 2005-03-30 株式会社三井ハイテック リードフレーム
JP3628971B2 (ja) * 2001-02-15 2005-03-16 松下電器産業株式会社 リードフレーム及びそれを用いた樹脂封止型半導体装置の製造方法
JP2007294715A (ja) * 2006-04-26 2007-11-08 Renesas Technology Corp 半導体装置の製造方法

Also Published As

Publication number Publication date
JP5144294B2 (ja) 2013-02-13
TW200939439A (en) 2009-09-16
JP2009188150A (ja) 2009-08-20

Similar Documents

Publication Publication Date Title
US6927483B1 (en) Semiconductor package exhibiting efficient lead placement
KR101587561B1 (ko) 리드프레임 어레이를 구비하는 집적회로 패키지 시스템
KR100859624B1 (ko) 반도체 장치의 제조 방법
US7638861B2 (en) Flip chip MLP with conductive ink
US20020031867A1 (en) Semiconductor device and process of production of same
US7888179B2 (en) Semiconductor device including a semiconductor chip which is mounted spaning a plurality of wiring boards and manufacturing method thereof
KR20130118781A (ko) 리드 프레임, 반도체 패키지, 및 그 제조 방법
TW201234504A (en) Semiconductor device package with electromagnetic shielding
JP2011077278A (ja) 半導体装置およびその製造方法
US8609467B2 (en) Lead frame and method for manufacturing circuit device using the same
KR20090086148A (ko) 리드 프레임 및 그것을 이용한 회로 장치의 제조 방법
US20170141014A1 (en) Semiconductor package with integrated heatsink
US8193643B2 (en) Semiconductor device and method for fabricating the same
KR100271657B1 (ko) 칼럼 리드형 반도체 패키지 및 그 제조방법
US8866296B2 (en) Semiconductor device comprising thin-film terminal with deformed portion
JP2010087129A (ja) 回路装置およびその製造方法
US8829685B2 (en) Circuit device having funnel shaped lead and method for manufacturing the same
KR100369202B1 (ko) 반도체 장치의 제조 방법
KR101132529B1 (ko) 회로 장치 및 그 제조 방법
KR20020073455A (ko) 반도체 장치의 제조 방법
JP2016162964A (ja) 半導体装置の製造方法および半導体装置
JP2011035142A (ja) 回路装置の製造方法
JP2009188147A (ja) 回路装置の製造方法
US7635642B2 (en) Integrated circuit package and method for producing it
JP2004335710A (ja) 半導体装置およびその製造方法

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
AMND Amendment
E601 Decision to refuse application
J201 Request for trial against refusal decision
AMND Amendment
B601 Maintenance of original decision after re-examination before a trial
J301 Trial decision

Free format text: TRIAL DECISION FOR APPEAL AGAINST DECISION TO DECLINE REFUSAL REQUESTED 20110401

Effective date: 20120220