KR20080043239A - 유기 강유전체막의 형성 방법, 기억 소자의 제조 방법,기억 장치, 및 전자 기기 - Google Patents

유기 강유전체막의 형성 방법, 기억 소자의 제조 방법,기억 장치, 및 전자 기기 Download PDF

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Publication number
KR20080043239A
KR20080043239A KR1020070114744A KR20070114744A KR20080043239A KR 20080043239 A KR20080043239 A KR 20080043239A KR 1020070114744 A KR1020070114744 A KR 1020070114744A KR 20070114744 A KR20070114744 A KR 20070114744A KR 20080043239 A KR20080043239 A KR 20080043239A
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KR
South Korea
Prior art keywords
film
organic ferroelectric
forming
crystallinity
ferroelectric film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1020070114744A
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English (en)
Korean (ko)
Inventor
히로시 다키구치
준이치 가라사와
Original Assignee
세이코 엡슨 가부시키가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 세이코 엡슨 가부시키가이샤 filed Critical 세이코 엡슨 가부시키가이샤
Publication of KR20080043239A publication Critical patent/KR20080043239A/ko
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0415—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having ferroelectric gate insulators
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
    • H10D64/662—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/689—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having ferroelectric layers

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Insulating Bodies (AREA)
  • Manufacture Of Macromolecular Shaped Articles (AREA)
  • Formation Of Insulating Films (AREA)
KR1020070114744A 2006-11-13 2007-11-12 유기 강유전체막의 형성 방법, 기억 소자의 제조 방법,기억 장치, 및 전자 기기 Withdrawn KR20080043239A (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2006307153 2006-11-13
JPJP-P-2006-00307153 2006-11-13
JP2007290164A JP2008147632A (ja) 2006-11-13 2007-11-07 有機強誘電体膜の形成方法、記憶素子の製造方法、記憶装置、および電子機器
JPJP-P-2007-00290164 2007-11-07

Publications (1)

Publication Number Publication Date
KR20080043239A true KR20080043239A (ko) 2008-05-16

Family

ID=39480511

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020070114744A Withdrawn KR20080043239A (ko) 2006-11-13 2007-11-12 유기 강유전체막의 형성 방법, 기억 소자의 제조 방법,기억 장치, 및 전자 기기

Country Status (3)

Country Link
JP (1) JP2008147632A (enExample)
KR (1) KR20080043239A (enExample)
CN (1) CN101188198A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101276560B1 (ko) * 2011-03-17 2013-06-24 한국과학기술원 강유전체 폴리머 나노도트 소자 및 그 제조를 위한 디웨팅 프로세스

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5957648B2 (ja) * 2009-09-14 2016-07-27 株式会社イデアルスター フッ化ビニリデンと、トリフルオロエチレン又はテトラフルオロエチレンとの共重合体とフラーレンとの混合膜及びその製造方法
JP2011159848A (ja) * 2010-02-02 2011-08-18 Toshiba Corp 固体撮像装置およびその製造方法
JP5926903B2 (ja) * 2011-08-22 2016-05-25 株式会社クレハ 所望のキュリー温度を有するポリマーの製造方法
US9293257B2 (en) 2011-11-09 2016-03-22 Japan Science And Technology Agency Solid-state electronic device including dielectric bismuth niobate film formed from solution
KR102043488B1 (ko) * 2013-03-14 2019-11-11 사우디 베이식 인더스트리즈 코포레이션 개선된 피로 및 항복 특성을 동반하는 강유전성 축전기
JP6229532B2 (ja) * 2014-02-21 2017-11-15 国立研究開発法人産業技術総合研究所 有機強誘電体薄膜の製造方法
JP2016171152A (ja) * 2015-03-12 2016-09-23 ペクセル・テクノロジーズ株式会社 ペロブスカイト化合物を用いた強誘電体メモリ素子およびその製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101276560B1 (ko) * 2011-03-17 2013-06-24 한국과학기술원 강유전체 폴리머 나노도트 소자 및 그 제조를 위한 디웨팅 프로세스

Also Published As

Publication number Publication date
CN101188198A (zh) 2008-05-28
JP2008147632A (ja) 2008-06-26

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Legal Events

Date Code Title Description
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 20071112

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid