KR20060132673A - Ｃｍｏｓ 실리사이드 금속 게이트 집적 방법 - Google Patents

Ｃｍｏｓ 실리사이드 금속 게이트 집적 방법 Download PDF

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Publication number
KR20060132673A
KR20060132673A KR1020067015375A KR20067015375A KR20060132673A KR 20060132673 A KR20060132673 A KR 20060132673A KR 1020067015375 A KR1020067015375 A KR 1020067015375A KR 20067015375 A KR20067015375 A KR 20067015375A KR 20060132673 A KR20060132673 A KR 20060132673A
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KR
South Korea
Prior art keywords
gate
metal
polysi
silicide
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
KR1020067015375A
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English (en)
Korean (ko)
Inventor
리키 에스 아모스
다이앤 씨 보이드
시릴 쥬니어 카브랄
리차드 디 카프란
자쿠브 티 케드지에르스키
빅터 쿠
우-형 이
잉 리
안다 씨 모쿠타
비자이 나라야난
안 엘 스티겐
마헤스와렌 수렌드라
Original Assignee
인터내셔널 비지네스 머신즈 코포레이션
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 인터내셔널 비지네스 머신즈 코포레이션 filed Critical 인터내셔널 비지네스 머신즈 코포레이션
Publication of KR20060132673A publication Critical patent/KR20060132673A/ko
Abandoned legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/069—Manufacture or treatment of conductive parts of the interconnections by forming self-aligned vias or self-aligned contact plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01306—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon
    • H10D64/01308—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon the conductor further comprising a non-elemental silicon additional conductive layer, e.g. a metal silicide layer formed by the reaction of silicon with an implanted metal
    • H10D64/0131—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon the conductor further comprising a non-elemental silicon additional conductive layer, e.g. a metal silicide layer formed by the reaction of silicon with an implanted metal the additional conductive layer comprising a silicide layer formed by the silicidation reaction between the layer of silicon with a metal layer which is not formed by metal implantation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01318—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN
    • H10D64/0132—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN the conductor being a metallic silicide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0172—Manufacturing their gate conductors
    • H10D84/0174—Manufacturing their gate conductors the gate conductors being silicided
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/021—Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
KR1020067015375A 2004-02-25 2005-02-22 Ｃｍｏｓ 실리사이드 금속 게이트 집적 방법 Abandoned KR20060132673A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/786,901 2004-02-25
US10/786,901 US7056782B2 (en) 2004-02-25 2004-02-25 CMOS silicide metal gate integration

Publications (1)

Publication Number Publication Date
KR20060132673A true KR20060132673A (ko) 2006-12-21

Family

ID=34861872

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020067015375A Abandoned KR20060132673A (ko) 2004-02-25 2005-02-22 Ｃｍｏｓ 실리사이드 금속 게이트 집적 방법

Country Status (7)

Country Link
US (3) US7056782B2 (https=)
EP (1) EP1726041A2 (https=)
JP (2) JP4917012B2 (https=)
KR (1) KR20060132673A (https=)
CN (1) CN1943027B (https=)
TW (1) TWI338349B (https=)
WO (1) WO2005083780A2 (https=)

Families Citing this family (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7611943B2 (en) * 2004-10-20 2009-11-03 Texas Instruments Incorporated Transistors, integrated circuits, systems, and processes of manufacture with improved work function modulation
JP2006294800A (ja) * 2005-04-08 2006-10-26 Toshiba Corp 半導体装置の製造方法
US20080296644A1 (en) * 2005-05-02 2008-12-04 Samsung Electronics Co., Ltd. Cmos image sensors and methods of fabricating same
KR100672812B1 (ko) * 2005-05-02 2007-01-22 삼성전자주식회사 이미지 센서와 그 제조 방법
US20060258074A1 (en) * 2005-05-12 2006-11-16 Texas Instruments Incorporated Methods that mitigate excessive source/drain silicidation in full gate silicidation metal gate flows
US7151023B1 (en) * 2005-08-01 2006-12-19 International Business Machines Corporation Metal gate MOSFET by full semiconductor metal alloy conversion
EP1772898A1 (en) * 2005-10-06 2007-04-11 Interuniversitair Microelektronica Centrum ( Imec) Method for forming a silicide gate
EP1801856A1 (en) * 2005-12-23 2007-06-27 Interuniversitair Microelektronica Centrum ( Imec) Method for gate electrode height control
US20080009134A1 (en) * 2006-07-06 2008-01-10 Tsung-Yu Hung Method for fabricating metal silicide
US20080277726A1 (en) * 2007-05-08 2008-11-13 Doris Bruce B Devices with Metal Gate, High-k Dielectric, and Butted Electrodes
US7880243B2 (en) * 2007-08-07 2011-02-01 International Business Machines Corporation Simple low power circuit structure with metal gate and high-k dielectric
KR100948294B1 (ko) * 2007-10-12 2010-03-17 주식회사 동부하이텍 반도체 소자의 제조방법
KR100935770B1 (ko) * 2007-11-26 2010-01-06 주식회사 동부하이텍 반도체 소자 및 이의 제조방법
CN101447421B (zh) * 2007-11-28 2010-09-22 中国科学院微电子研究所 一种制备金属栅电极的方法
US7790541B2 (en) * 2007-12-04 2010-09-07 International Business Machines Corporation Method and structure for forming multiple self-aligned gate stacks for logic devices
US8097500B2 (en) * 2008-01-14 2012-01-17 International Business Machines Corporation Method and apparatus for fabricating a high-performance band-edge complementary metal-oxide-semiconductor device
US7723192B2 (en) * 2008-03-14 2010-05-25 Advanced Micro Devices, Inc. Integrated circuit long and short channel metal gate devices and method of manufacture
US7749898B2 (en) * 2008-06-24 2010-07-06 Globalfoundries Inc. Silicide interconnect structure
US9236448B2 (en) * 2008-09-02 2016-01-12 Cypress Semiconductor Corporation Method for achieving very small feature size in semiconductor device by undertaking silicide sidewall growth and etching
US8008145B2 (en) * 2008-09-10 2011-08-30 Taiwan Semiconductor Manufacturing Company, Ltd. High-K metal gate structure fabrication method including hard mask
US7981801B2 (en) * 2008-09-12 2011-07-19 Taiwan Semiconductor Manufacturing Company, Ltd. Chemical mechanical polishing (CMP) method for gate last process
US7977181B2 (en) * 2008-10-06 2011-07-12 Taiwan Semiconductor Manufacturing Company, Ltd. Method for gate height control in a gate last process
US8629506B2 (en) * 2009-03-19 2014-01-14 International Business Machines Corporation Replacement gate CMOS
DE102009055395B4 (de) * 2009-12-30 2011-12-29 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Vordotiertes Halbleitermaterial für eine Metallgateelektrodenstruktur mit großem ε von p-und n-Kanaltransistoren
US8222100B2 (en) * 2010-01-15 2012-07-17 International Business Machines Corporation CMOS circuit with low-k spacer and stress liner
US8039388B1 (en) 2010-03-24 2011-10-18 Taiwam Semiconductor Manufacturing Company, Ltd. Main spacer trim-back method for replacement gate process
CN102208341A (zh) * 2010-03-31 2011-10-05 上海华虹Nec电子有限公司 降低多晶硅栅极电阻的方法
US8497210B2 (en) * 2010-10-04 2013-07-30 International Business Machines Corporation Shallow trench isolation chemical mechanical planarization
US8420473B2 (en) 2010-12-06 2013-04-16 International Business Machines Corporation Replacement gate devices with barrier metal for simultaneous processing
US8536656B2 (en) * 2011-01-10 2013-09-17 International Business Machines Corporation Self-aligned contacts for high k/metal gate process flow
US8377790B2 (en) 2011-01-27 2013-02-19 International Business Machines Corporation Method of fabricating an embedded polysilicon resistor and an embedded eFuse isolated from a substrate
US9269634B2 (en) 2011-05-16 2016-02-23 Globalfoundries Inc. Self-aligned metal gate CMOS with metal base layer and dummy gate structure
CN102420144A (zh) * 2011-06-15 2012-04-18 上海华力微电子有限公司 一种改善先栅极工艺高k栅电介质nmos hci方法
US8765586B2 (en) 2011-12-20 2014-07-01 Globalfoundries Inc. Methods of forming metal silicide regions on semiconductor devices
US9041076B2 (en) 2013-02-03 2015-05-26 International Business Machines Corporation Partial sacrificial dummy gate with CMOS device with high-k metal gate
CN103855007A (zh) * 2012-11-30 2014-06-11 中国科学院微电子研究所 P型mosfet的制造方法
CN103855006A (zh) 2012-11-30 2014-06-11 中国科学院微电子研究所 半导体器件的制造方法
US9419126B2 (en) * 2013-03-15 2016-08-16 GlobalFoundries, Inc. Integrated circuits and methods for fabricating integrated circuits with active area protection
CN103943482B (zh) * 2014-04-22 2017-08-08 上海华力微电子有限公司 降低多晶硅栅极与活化区镍硅化物厚度比的方法
US10050147B2 (en) 2015-07-24 2018-08-14 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US10354880B2 (en) * 2017-04-05 2019-07-16 International Business Machines Corporation Sidewall spacer with controlled geometry
CN110233106B (zh) * 2018-03-05 2022-10-25 中芯国际集成电路制造(北京)有限公司 半导体结构及其形成方法
JP7101090B2 (ja) * 2018-09-12 2022-07-14 株式会社東芝 半導体装置
CN113130393B (zh) * 2020-01-16 2025-04-25 中芯国际集成电路制造(上海)有限公司 半导体结构的形成方法

Family Cites Families (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2582445B1 (fr) 1985-05-21 1988-04-08 Efcis Procede de fabrication de transistors mos a electrodes de siliciure metallique
JPS62154784A (ja) * 1985-12-27 1987-07-09 Hitachi Ltd 半導体装置
JPH0521458A (ja) * 1991-07-11 1993-01-29 Nec Corp 半導体装置およびその製造方法
US5733812A (en) 1993-11-15 1998-03-31 Matsushita Electric Industrial Co., Ltd. Semiconductor device with a field-effect transistor having a lower resistance impurity diffusion layer, and method of manufacturing the same
JP3596062B2 (ja) * 1995-01-20 2004-12-02 ソニー株式会社 コンタクト構造の形成方法
US6060387A (en) * 1995-11-20 2000-05-09 Compaq Computer Corporation Transistor fabrication process in which a contact metallization is formed with different silicide thickness over gate interconnect material and transistor source/drain regions
US6482626B2 (en) 1996-02-05 2002-11-19 Genentech, Inc. Human DNase
JPH1187705A (ja) * 1997-09-11 1999-03-30 Sharp Corp 静電的破壊保護素子及びその製造方法
JP2970620B2 (ja) * 1997-10-20 1999-11-02 日本電気株式会社 半導体装置の製造方法
JPH11191594A (ja) * 1997-10-21 1999-07-13 Sony Corp 半導体装置の製造方法
US6022769A (en) * 1997-12-23 2000-02-08 Texas Instruments -- Acer Incorporated Method of making self-aligned silicided MOS transistor with ESD protection improvement
JP4326606B2 (ja) * 1998-03-26 2009-09-09 株式会社ルネサステクノロジ 半導体装置およびその製造方法
US6140216A (en) * 1998-04-14 2000-10-31 Advanced Micro Devices, Inc. Post etch silicide formation using dielectric etchback after global planarization
US6124610A (en) * 1998-06-26 2000-09-26 Advanced Micro Devices, Inc. Isotropically etching sidewall spacers to be used for both an NMOS source/drain implant and a PMOS LDD implant
JP2000077535A (ja) * 1998-09-02 2000-03-14 Hitachi Ltd 半導体装置及びその製造方法
US6100145A (en) * 1998-11-05 2000-08-08 Advanced Micro Devices, Inc. Silicidation with silicon buffer layer and silicon spacers
US6153485A (en) * 1998-11-09 2000-11-28 Chartered Semiconductor Manufacturing Ltd. Salicide formation on narrow poly lines by pulling back of spacer
JP2000252462A (ja) * 1999-03-01 2000-09-14 Toshiba Corp Ｍｉｓ型半導体装置及びその製造方法
US6238982B1 (en) * 1999-04-13 2001-05-29 Advanced Micro Devices Multiple threshold voltage semiconductor device fabrication technology
US6190961B1 (en) 1999-09-22 2001-02-20 International Business Machines Corporation Fabricating a square spacer
FR2804793B1 (fr) 2000-02-07 2003-07-04 St Microelectronics Sa Procede d'ajustement de la valeur de resistance de grille d'un transistor d'un circuit integre et circuit integre correspondant
US6458702B1 (en) 2000-03-09 2002-10-01 Tower Semiconductor Ltd. Methods for making semiconductor chip having both self aligned silicide regions and non-self aligned silicide regions
FR2810157B1 (fr) * 2000-06-09 2002-08-16 Commissariat Energie Atomique Procede de realisation d'un composant electronique a source, drain et grille auto-allignes, en architecture damascene
JP3961211B2 (ja) * 2000-10-31 2007-08-22 株式会社東芝 半導体装置の製造方法
JP2002217411A (ja) 2001-01-17 2002-08-02 Hitachi Ltd 半導体装置の製造方法
US20020123222A1 (en) 2001-03-01 2002-09-05 Bing-Chang Wu Method of fabricating a salicide layer
US6596576B2 (en) * 2001-04-10 2003-07-22 Applied Materials, Inc. Limiting hydrogen ion diffusion using multiple layers of SiO2 and Si3N4
JP3485103B2 (ja) * 2001-04-19 2004-01-13 セイコーエプソン株式会社 Ｍｏｓ型トランジスタ及びその製造方法
KR20020083795A (ko) * 2001-04-30 2002-11-04 삼성전자 주식회사 자기정렬 실리사이드 기술을 사용하는 모스 트랜지스터의제조방법
JP2003142597A (ja) * 2001-11-01 2003-05-16 Hitachi Ltd 半導体装置の製造方法
US20030141565A1 (en) 2002-01-28 2003-07-31 Fumihiko Hirose Diode
US6599831B1 (en) * 2002-04-30 2003-07-29 Advanced Micro Devices, Inc. Metal gate electrode using silicidation and method of formation thereof
US6656764B1 (en) 2002-05-15 2003-12-02 Taiwan Semiconductor Manufacturing Company Process for integration of a high dielectric constant gate insulator layer in a CMOS device
KR100438788B1 (ko) 2002-06-12 2004-07-05 삼성전자주식회사 반도체 장치 및 그의 제조방법
US6657244B1 (en) * 2002-06-28 2003-12-02 International Business Machines Corporation Structure and method to reduce silicon substrate consumption and improve gate sheet resistance during silicide formation
US6787464B1 (en) * 2002-07-02 2004-09-07 Advanced Micro Devices, Inc. Method of forming silicide layers over a plurality of semiconductor devices
US6974729B2 (en) * 2002-07-16 2005-12-13 Interuniversitair Microelektronica Centrum (Imec) Integrated semiconductor fin device and a method for manufacturing such device
US6924184B2 (en) * 2003-03-21 2005-08-02 Freescale Semiconductor, Inc. Semiconductor device and method for forming a semiconductor device using post gate stack planarization
US6867130B1 (en) * 2003-05-28 2005-03-15 Advanced Micro Devices, Inc. Enhanced silicidation of polysilicon gate electrodes
US6905922B2 (en) * 2003-10-03 2005-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Dual fully-silicided gate MOSFETs

Also Published As

Publication number Publication date
JP2007524252A (ja) 2007-08-23
US7411227B2 (en) 2008-08-12
US7056782B2 (en) 2006-06-06
US20060189061A1 (en) 2006-08-24
WO2005083780A3 (en) 2005-12-08
US20080254622A1 (en) 2008-10-16
CN1943027B (zh) 2010-09-29
CN1943027A (zh) 2007-04-04
JP2012054555A (ja) 2012-03-15
TW200531216A (en) 2005-09-16
JP5574441B2 (ja) 2014-08-20
US7655557B2 (en) 2010-02-02
US20050186747A1 (en) 2005-08-25
TWI338349B (en) 2011-03-01
EP1726041A2 (en) 2006-11-29
JP4917012B2 (ja) 2012-04-18
WO2005083780A2 (en) 2005-09-09

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