KR20060120078A - 게이트 유발 접합 누설 전류를 사용하는 플래시 메모리프로그래밍 - Google Patents

게이트 유발 접합 누설 전류를 사용하는 플래시 메모리프로그래밍 Download PDF

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Publication number
KR20060120078A
KR20060120078A KR1020067008923A KR20067008923A KR20060120078A KR 20060120078 A KR20060120078 A KR 20060120078A KR 1020067008923 A KR1020067008923 A KR 1020067008923A KR 20067008923 A KR20067008923 A KR 20067008923A KR 20060120078 A KR20060120078 A KR 20060120078A
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South Korea
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gate
bias
substrate
applying
active region
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KR1020067008923A
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English (en)
Korean (ko)
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제프리 더블유. 루체
찬-수이 팡
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샌디스크 코포레이션
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0425—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a merged floating gate and select transistor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
KR1020067008923A 2003-11-07 2004-11-04 게이트 유발 접합 누설 전류를 사용하는 플래시 메모리프로그래밍 Withdrawn KR20060120078A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/703,717 US7057931B2 (en) 2003-11-07 2003-11-07 Flash memory programming using gate induced junction leakage current
US10/703,717 2003-11-07

Publications (1)

Publication Number Publication Date
KR20060120078A true KR20060120078A (ko) 2006-11-24

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KR1020067008923A Withdrawn KR20060120078A (ko) 2003-11-07 2004-11-04 게이트 유발 접합 누설 전류를 사용하는 플래시 메모리프로그래밍

Country Status (7)

Country Link
US (1) US7057931B2 (enExample)
EP (1) EP1687826A2 (enExample)
JP (1) JP2007511076A (enExample)
KR (1) KR20060120078A (enExample)
CN (1) CN1938785A (enExample)
TW (1) TWI274348B (enExample)
WO (1) WO2005048269A2 (enExample)

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US8248853B2 (en) 2008-11-12 2012-08-21 Samsung Electronics Co., Ltd. Methods of programming non-volatile flash memory devices by applying a higher voltage level to a selected word line than to a word line neighboring the selected word line
KR101503875B1 (ko) * 2008-03-17 2015-03-25 삼성전자주식회사 단채널 효과를 억제할 수 있는 반도체 장치 및 그 제조방법

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JP5250182B2 (ja) * 2005-10-28 2013-07-31 シャープ株式会社 不揮発性メモリ装置およびその駆動方法
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US8384147B2 (en) * 2011-04-29 2013-02-26 Silicon Storage Technology, Inc. High endurance non-volatile memory cell and array
US8711636B2 (en) * 2011-05-13 2014-04-29 Silicon Storage Technology, Inc. Method of operating a split gate flash memory cell with coupling gate
US8670277B2 (en) 2011-07-27 2014-03-11 Infineon Technologies Ag Memory and method for programming memory cells
US9064551B2 (en) 2012-05-15 2015-06-23 Micron Technology, Inc. Apparatuses and methods for coupling load current to a common source
US8976594B2 (en) 2012-05-15 2015-03-10 Micron Technology, Inc. Memory read apparatus and methods
US9064577B2 (en) 2012-12-06 2015-06-23 Micron Technology, Inc. Apparatuses and methods to control body potential in memory operations
US8995188B2 (en) 2013-04-17 2015-03-31 Micron Technology, Inc. Sharing support circuitry in a memory
CN104637537B (zh) * 2014-11-17 2019-02-19 上海华力微电子有限公司 一种闪存器件及其编程方法
JP6739327B2 (ja) * 2016-12-27 2020-08-12 ルネサスエレクトロニクス株式会社 半導体装置
US10176880B1 (en) 2017-07-01 2019-01-08 Intel Corporation Selective body reset operation for three dimensional (3D) NAND memory
TWI824233B (zh) * 2020-02-12 2023-12-01 美商新思科技股份有限公司 具有漏電流中的統計變化之動態隨機存取記憶體通路電晶體的設計
CN114695370B (zh) * 2022-05-31 2023-03-24 广州粤芯半导体技术有限公司 半导体结构及其制备方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101503875B1 (ko) * 2008-03-17 2015-03-25 삼성전자주식회사 단채널 효과를 억제할 수 있는 반도체 장치 및 그 제조방법
US8248853B2 (en) 2008-11-12 2012-08-21 Samsung Electronics Co., Ltd. Methods of programming non-volatile flash memory devices by applying a higher voltage level to a selected word line than to a word line neighboring the selected word line

Also Published As

Publication number Publication date
US7057931B2 (en) 2006-06-06
WO2005048269A2 (en) 2005-05-26
TW200537504A (en) 2005-11-16
WO2005048269A3 (en) 2005-07-28
CN1938785A (zh) 2007-03-28
JP2007511076A (ja) 2007-04-26
TWI274348B (en) 2007-02-21
US20050099849A1 (en) 2005-05-12
EP1687826A2 (en) 2006-08-09

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PA0105 International application

Patent event date: 20060508

Patent event code: PA01051R01D

Comment text: International Patent Application

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid