KR20060053426A - 메모리 장치의 리프레쉬 수행 방법 - Google Patents
메모리 장치의 리프레쉬 수행 방법 Download PDFInfo
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- KR20060053426A KR20060053426A KR1020040093117A KR20040093117A KR20060053426A KR 20060053426 A KR20060053426 A KR 20060053426A KR 1020040093117 A KR1020040093117 A KR 1020040093117A KR 20040093117 A KR20040093117 A KR 20040093117A KR 20060053426 A KR20060053426 A KR 20060053426A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40611—External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40615—Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40618—Refresh operations over multiple banks or interleaving
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40622—Partial refresh of memory arrays
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
Abstract
Description
Claims (4)
- N 개의 뱅크를 갖는 메모리 장치의 리프레쉬 수행 방법에 있어서,상기 N 개의 뱅크를 모두 리프레쉬하는 경우에는 누적적 리프레쉬 동작을 수행하며,상기 N 개의 뱅크중 i 개의 뱅크(여기서, 1<i≤N-1 )를 리프레쉬하는 경우에는 PASR 방식에 의하여 버스트 리프레쉬 동작을 수행하는 것을 특징으로 하는 메모리 장치의 리프레쉬 수행 방법.
- 제 1 항에 있어서,상기 리프레쉬 동작은 셀프 리프레쉬 모드에서 이루어지는 것을 특징으로 하는 메모리 장치의 리프레쉬 수행 방법.
- N 개의 뱅크를 갖는 메모리 장치의 리프레쉬 수행 방법에 있어서,셀프 리프레쉬 모드에서, 상기 N 개의 뱅크 모두를 리프레쉬하는 경우에는 상기 N개의 뱅크를 순차적으로 리프레쉬하는 누적적 리프레쉬 방식에 의하여 리프레쉬 동작을 수행하며, 상기 N 개의 뱅크중 i 개의 뱅크(여기서, 1<i≤N-1 )를 리프레쉬하는 경우에는 PASR 방식에 의하여 리프레쉬 동작을 수행하며,오토 리프레쉬 모드에서는 상기 누적적 리프레쉬 방식에 의하여 리프레쉬 동작을 수행하는 것을 특징으로 하는 N 개의 뱅크를 갖는 메모리 장치의 리프레쉬 수 행 방법.
- N 개의 뱅크를 갖는 메모리 장치의 리프레쉬 수행 방법에 있어서,(a)리프레쉬 커맨드를 수신하는 단계;(b)상기 리프레쉬 커맨드에 의하여 발생하며 리프레쉬될 N 개의 뱅크중 제 1 뱅크를 선택하는 신호를 발생하는 단계;(c)상기 리프레쉬 커맨드 및 PASR 코드를 수신하여, 상기 N 개의 뱅크에 대하여 누적적 리프레쉬 동작을 수행할 것인지 PASR 방식에 의한 버스트 리프레쉬 동작을 수행할 것인지를 판별하는 신호를 발생하는 단계;(d)상기 (b)및 (c)단계의 출력신호를 수신하여 리프레쉬될 상기 제 1 뱅크의 어드레스 신호를 생성하는 단계;(e)상기 제 1 뱅크 어드레스 신호에 의하여 지정된 상기 제 1 뱅크를 리프레쉬하는 신호를 발생하는 단계(f)상기 단계(e)에서 발생된 상기 리프레쉬 신호에 의하여 리프레쉬 동작을 수행하는 단계;를 구비하며상기 단계(c)에 의하여 상기 누적적 리프레쉬 동작이 이루어지는 경우에는 상기 단계 (b),(d),(e),(f)를 반복 수행하며,상기 단계(c)에 의하여 상기 버스트 리프레쉬 동작이 이루어지는 경우에는 리프레쉬될 뱅크가 모두 선택될까지 상기 단계 (b),(d),(e)를 반복 수행한 후, 상 기 (e)단계를 수행하는 것을 특징으로 하는 메모리 장치의 리프레쉬 수행 방법.
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020040093117A KR100608370B1 (ko) | 2004-11-15 | 2004-11-15 | 메모리 장치의 리프레쉬 수행 방법 |
DE102005020894A DE102005020894A1 (de) | 2004-11-15 | 2005-05-04 | Verfahren zum Auffrischen einer Speichervorrichtung, welche PASR und stapel-artige Auffrischungsschematas aufweisen |
JP2005134894A JP2006147123A (ja) | 2004-11-15 | 2005-05-06 | メモリ装置のリフレッシュ方法 |
TW094114972A TWI268509B (en) | 2004-11-15 | 2005-05-09 | Method of refreshing a memory device utilizing PASR and piled refresh schemes |
US11/125,687 US7149140B2 (en) | 2004-11-15 | 2005-05-10 | Method of refreshing a memory device utilizing PASR and piled refresh schemes |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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KR1020040093117A KR100608370B1 (ko) | 2004-11-15 | 2004-11-15 | 메모리 장치의 리프레쉬 수행 방법 |
Publications (2)
Publication Number | Publication Date |
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KR20060053426A true KR20060053426A (ko) | 2006-05-22 |
KR100608370B1 KR100608370B1 (ko) | 2006-08-08 |
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KR1020040093117A KR100608370B1 (ko) | 2004-11-15 | 2004-11-15 | 메모리 장치의 리프레쉬 수행 방법 |
Country Status (5)
Country | Link |
---|---|
US (1) | US7149140B2 (ko) |
JP (1) | JP2006147123A (ko) |
KR (1) | KR100608370B1 (ko) |
DE (1) | DE102005020894A1 (ko) |
TW (1) | TWI268509B (ko) |
Cited By (2)
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KR100896242B1 (ko) * | 2006-12-22 | 2009-05-08 | 후지쯔 마이크로일렉트로닉스 가부시키가이샤 | 메모리 장치, 메모리 컨트롤러 및 메모리 시스템 |
US8395957B2 (en) | 2010-08-30 | 2013-03-12 | Hynix Semiconductor Inc. | Circuit and method for controlling self-refresh operation in semiconductor memory device |
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JP2007035151A (ja) * | 2005-07-26 | 2007-02-08 | Elpida Memory Inc | 半導体メモリ装置およびメモリシステムのリフレッシュ制御方法 |
JP4299849B2 (ja) | 2006-08-22 | 2009-07-22 | エルピーダメモリ株式会社 | 半導体記憶装置及びそのリフレッシュ制御方法 |
KR100947973B1 (ko) | 2008-01-14 | 2010-03-15 | 삼성에스디아이 주식회사 | 배터리 팩 |
US7969807B2 (en) * | 2008-03-05 | 2011-06-28 | Qimonda Ag | Memory that retains data when switching partial array self refresh settings |
KR101003121B1 (ko) | 2008-12-23 | 2010-12-22 | 주식회사 하이닉스반도체 | 반도체 메모리 장치의 리프레쉬 회로 |
US8468295B2 (en) * | 2009-12-02 | 2013-06-18 | Dell Products L.P. | System and method for reducing power consumption of memory |
US8392650B2 (en) | 2010-04-01 | 2013-03-05 | Intel Corporation | Fast exit from self-refresh state of a memory device |
US8484410B2 (en) * | 2010-04-12 | 2013-07-09 | Intel Corporation | Method to stagger self refreshes |
US20110296098A1 (en) | 2010-06-01 | 2011-12-01 | Dell Products L.P. | System and Method for Reducing Power Consumption of Memory |
US8411523B2 (en) | 2010-09-24 | 2013-04-02 | Intel Corporation | Reduced current requirements for DRAM self-refresh modes via staggered refresh operations of subsets of memory banks or rows |
KR20130024158A (ko) | 2011-08-30 | 2013-03-08 | 에스케이하이닉스 주식회사 | 반도체메모리장치 및 반도체메모리장치의 리프레쉬 방법 |
TWI503662B (zh) | 2012-12-27 | 2015-10-11 | Ind Tech Res Inst | 記憶體控制裝置及方法 |
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US10490251B2 (en) | 2017-01-30 | 2019-11-26 | Micron Technology, Inc. | Apparatuses and methods for distributing row hammer refresh events across a memory device |
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US10573370B2 (en) | 2018-07-02 | 2020-02-25 | Micron Technology, Inc. | Apparatus and methods for triggering row hammer address sampling |
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US11309010B2 (en) | 2020-08-14 | 2022-04-19 | Micron Technology, Inc. | Apparatuses, systems, and methods for memory directed access pause |
US11380382B2 (en) | 2020-08-19 | 2022-07-05 | Micron Technology, Inc. | Refresh logic circuit layout having aggressor detector circuit sampling circuit and row hammer refresh control circuit |
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-
2004
- 2004-11-15 KR KR1020040093117A patent/KR100608370B1/ko active IP Right Grant
-
2005
- 2005-05-04 DE DE102005020894A patent/DE102005020894A1/de not_active Withdrawn
- 2005-05-06 JP JP2005134894A patent/JP2006147123A/ja active Pending
- 2005-05-09 TW TW094114972A patent/TWI268509B/zh not_active IP Right Cessation
- 2005-05-10 US US11/125,687 patent/US7149140B2/en active Active
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100896242B1 (ko) * | 2006-12-22 | 2009-05-08 | 후지쯔 마이크로일렉트로닉스 가부시키가이샤 | 메모리 장치, 메모리 컨트롤러 및 메모리 시스템 |
US8004921B2 (en) | 2006-12-22 | 2011-08-23 | Fujitsu Semiconductor Limited | Memory device, memory controller and memory system |
US8077537B2 (en) | 2006-12-22 | 2011-12-13 | Fujitsu Semiconductor Limited | Memory device, memory controller and memory system |
US8395957B2 (en) | 2010-08-30 | 2013-03-12 | Hynix Semiconductor Inc. | Circuit and method for controlling self-refresh operation in semiconductor memory device |
Also Published As
Publication number | Publication date |
---|---|
KR100608370B1 (ko) | 2006-08-08 |
TW200615954A (en) | 2006-05-16 |
TWI268509B (en) | 2006-12-11 |
US7149140B2 (en) | 2006-12-12 |
US20060104139A1 (en) | 2006-05-18 |
DE102005020894A1 (de) | 2006-05-24 |
JP2006147123A (ja) | 2006-06-08 |
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