JP2006147123A - メモリ装置のリフレッシュ方法 - Google Patents
メモリ装置のリフレッシュ方法 Download PDFInfo
- Publication number
- JP2006147123A JP2006147123A JP2005134894A JP2005134894A JP2006147123A JP 2006147123 A JP2006147123 A JP 2006147123A JP 2005134894 A JP2005134894 A JP 2005134894A JP 2005134894 A JP2005134894 A JP 2005134894A JP 2006147123 A JP2006147123 A JP 2006147123A
- Authority
- JP
- Japan
- Prior art keywords
- refresh
- signal
- bank
- banks
- memory device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40611—External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40615—Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40618—Refresh operations over multiple banks or interleaving
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40622—Partial refresh of memory arrays
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
Abstract
【課題手段】 N個のバンクを有するメモリ装置のリフレッシュ方法において、セルフリフレッシュモードでは、N個のバンクすべてをリフレッシュする場合には、N個のバンクを順次リフレッシュするパイルドリフレッシュ方式によってリフレッシュ動作を実行し、N個のバンクのうち、i個(1≦i≦N−1)のバンクをリフレッシュする場合には、PASR方式によってリフレッシュ動作を実行し、オートリフレッシュモードでは、パイルドリフレッシュ方式によってリフレッシュ動作を実行する。
【選択図】図3
Description
306 バーストリフレッシュ信号発生部
307 バンクアクティブ及びバンクプリチャージ信号発生部
601、604 ノアゲート
602 ナンドゲート
603 インバータ
605 インバータ
Claims (4)
- N個のバンクを有するメモリ装置のリフレッシュ方法において、
前記N個のバンクをすべてリフレッシュする場合には、パイルドリフレッシュ動作を実行し、
前記N個のバンクのうち、i個(1≦i≦N−1)のバンクをリフレッシュする場合には、パーシャルアレイセルフリフレッシュ(PASR)方式によってバーストリフレッシュ動作を実行することを特徴とするメモリ装置のリフレッシュ方法。 - 前記リフレッシュ動作を、セルフリフレッシュモードで実行することを特徴とする請求項1に記載のメモリ装置のリフレッシュ方法。
- N個のバンクを有するメモリ装置のリフレッシュ方法において、
セルフリフレッシュモードでは、前記N個のバンクすべてをリフレッシュする場合には、前記N個のバンクを順次リフレッシュするパイルドリフレッシュ方式によってリフレッシュ動作を実行し、前記N個のバンクのうち、i個(1≦i≦N−1)のバンクをリフレッシュする場合には、パーシャルアレイセルフリフレッシュ(PASR)方式によってリフレッシュ動作を実行し、
オートリフレッシュモードでは、前記パイルドリフレッシュ方式によってリフレッシュ動作を実行することを特徴とするN個のバンクを有するメモリ装置のリフレッシュ方法。 - N個のバンクを有するメモリ装置のリフレッシュ方法において、
(a)リフレッシュコマンドを受信するステップと、
(b)該リフレッシュコマンドによって、リフレッシュされるN個のバンクのうち、第1バンクを選択する信号を生成するステップと、
(c)前記リフレッシュコマンド及びパーシャルアレイセルフリフレッシュ(PASR)コードを受信して、前記N個のバンクに対して、パイルドリフレッシュ動作を実行するか、またはPASR方式によるバーストリフレッシュ動作を実行するかを判別する信号を生成するステップと、
(d)前記ステップ(b)及び(c)における出力信号を受信して、リフレッシュされる前記第1バンクのアドレス信号を生成するステップと、
(e)前記第1バンクアドレス信号によって指定された前記第1バンクをリフレッシュするリフレッシュ信号を生成するステップと、
(f)前記ステップ(e)で生成された前記リフレッシュ信号によってリフレッシュ動作を実行するステップとを含み、
前記ステップ(c)において前記パイルドリフレッシュ動作を判別する信号が生成された場合には、前記ステップ(b)、(d)、(e)及び(f)を反復して実行し、
前記ステップ(c)において前記バーストリフレッシュ動作を判別する信号が生成された場合には、リフレッシュされるバンクがすべて選択されるまで、前記ステップ(b)、(d)及び(e)を反復して実行した後、前記ステップ(f)を実行することを特徴とするメモリ装置のリフレッシュ方法。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020040093117A KR100608370B1 (ko) | 2004-11-15 | 2004-11-15 | 메모리 장치의 리프레쉬 수행 방법 |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2006147123A true JP2006147123A (ja) | 2006-06-08 |
Family
ID=36313914
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005134894A Pending JP2006147123A (ja) | 2004-11-15 | 2005-05-06 | メモリ装置のリフレッシュ方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US7149140B2 (ja) |
JP (1) | JP2006147123A (ja) |
KR (1) | KR100608370B1 (ja) |
DE (1) | DE102005020894A1 (ja) |
TW (1) | TWI268509B (ja) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7486584B2 (en) | 2006-08-22 | 2009-02-03 | Elpida Memory, Inc. | Semiconductor memory device and refresh control method thereof |
EP2079126A1 (en) | 2008-01-14 | 2009-07-15 | Samsung SDI Co., Ltd. | Impact Resistant Battery Pack |
US7881109B2 (en) | 2008-12-23 | 2011-02-01 | Hynix Semiconductor Inc. | Refresh circuit of semiconductor memory apparatus |
Families Citing this family (34)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007035151A (ja) * | 2005-07-26 | 2007-02-08 | Elpida Memory Inc | 半導体メモリ装置およびメモリシステムのリフレッシュ制御方法 |
US20080151670A1 (en) | 2006-12-22 | 2008-06-26 | Tomohiro Kawakubo | Memory device, memory controller and memory system |
US7969807B2 (en) * | 2008-03-05 | 2011-06-28 | Qimonda Ag | Memory that retains data when switching partial array self refresh settings |
US8468295B2 (en) * | 2009-12-02 | 2013-06-18 | Dell Products L.P. | System and method for reducing power consumption of memory |
US8392650B2 (en) | 2010-04-01 | 2013-03-05 | Intel Corporation | Fast exit from self-refresh state of a memory device |
US8484410B2 (en) | 2010-04-12 | 2013-07-09 | Intel Corporation | Method to stagger self refreshes |
US20110296098A1 (en) | 2010-06-01 | 2011-12-01 | Dell Products L.P. | System and Method for Reducing Power Consumption of Memory |
KR101190741B1 (ko) | 2010-08-30 | 2012-10-12 | 에스케이하이닉스 주식회사 | 반도체 메모리 장치의 셀프 리프레시 제어회로 및 제어 방법 |
US8411523B2 (en) | 2010-09-24 | 2013-04-02 | Intel Corporation | Reduced current requirements for DRAM self-refresh modes via staggered refresh operations of subsets of memory banks or rows |
KR20130024158A (ko) | 2011-08-30 | 2013-03-08 | 에스케이하이닉스 주식회사 | 반도체메모리장치 및 반도체메모리장치의 리프레쉬 방법 |
TWI503662B (zh) * | 2012-12-27 | 2015-10-11 | Ind Tech Res Inst | 記憶體控制裝置及方法 |
KR102289001B1 (ko) * | 2014-06-09 | 2021-08-13 | 삼성전자주식회사 | 솔리드 스테이드 드라이브 및 그것의 동작 방법 |
KR20160013624A (ko) * | 2014-07-28 | 2016-02-05 | 에스케이하이닉스 주식회사 | 리프레쉬 회로 |
KR102372888B1 (ko) | 2015-06-15 | 2022-03-10 | 삼성전자주식회사 | 저장 장치의 온도별 데이터 관리 방법 |
KR102321793B1 (ko) | 2015-08-12 | 2021-11-08 | 삼성전자주식회사 | 플렉시블 리프레쉬 스킵 영역을 운영하는 반도체 메모리 장치 |
US10490251B2 (en) | 2017-01-30 | 2019-11-26 | Micron Technology, Inc. | Apparatuses and methods for distributing row hammer refresh events across a memory device |
US11017833B2 (en) | 2018-05-24 | 2021-05-25 | Micron Technology, Inc. | Apparatuses and methods for pure-time, self adopt sampling for row hammer refresh sampling |
US10573370B2 (en) | 2018-07-02 | 2020-02-25 | Micron Technology, Inc. | Apparatus and methods for triggering row hammer address sampling |
US10685696B2 (en) | 2018-10-31 | 2020-06-16 | Micron Technology, Inc. | Apparatuses and methods for access based refresh timing |
WO2020117686A1 (en) | 2018-12-03 | 2020-06-11 | Micron Technology, Inc. | Semiconductor device performing row hammer refresh operation |
CN111354393B (zh) | 2018-12-21 | 2023-10-20 | 美光科技公司 | 用于目标刷新操作的时序交错的设备和方法 |
US10957377B2 (en) | 2018-12-26 | 2021-03-23 | Micron Technology, Inc. | Apparatuses and methods for distributed targeted refresh operations |
US11615831B2 (en) * | 2019-02-26 | 2023-03-28 | Micron Technology, Inc. | Apparatuses and methods for memory mat refresh sequencing |
US11227649B2 (en) | 2019-04-04 | 2022-01-18 | Micron Technology, Inc. | Apparatuses and methods for staggered timing of targeted refresh operations |
US11069393B2 (en) | 2019-06-04 | 2021-07-20 | Micron Technology, Inc. | Apparatuses and methods for controlling steal rates |
US10978132B2 (en) | 2019-06-05 | 2021-04-13 | Micron Technology, Inc. | Apparatuses and methods for staggered timing of skipped refresh operations |
US11302374B2 (en) | 2019-08-23 | 2022-04-12 | Micron Technology, Inc. | Apparatuses and methods for dynamic refresh allocation |
US11302377B2 (en) | 2019-10-16 | 2022-04-12 | Micron Technology, Inc. | Apparatuses and methods for dynamic targeted refresh steals |
US11309010B2 (en) | 2020-08-14 | 2022-04-19 | Micron Technology, Inc. | Apparatuses, systems, and methods for memory directed access pause |
US11380382B2 (en) | 2020-08-19 | 2022-07-05 | Micron Technology, Inc. | Refresh logic circuit layout having aggressor detector circuit sampling circuit and row hammer refresh control circuit |
US11348631B2 (en) | 2020-08-19 | 2022-05-31 | Micron Technology, Inc. | Apparatuses, systems, and methods for identifying victim rows in a memory device which cannot be simultaneously refreshed |
US11557331B2 (en) | 2020-09-23 | 2023-01-17 | Micron Technology, Inc. | Apparatuses and methods for controlling refresh operations |
US11222686B1 (en) | 2020-11-12 | 2022-01-11 | Micron Technology, Inc. | Apparatuses and methods for controlling refresh timing |
US11264079B1 (en) | 2020-12-18 | 2022-03-01 | Micron Technology, Inc. | Apparatuses and methods for row hammer based cache lockdown |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001035152A (ja) * | 1999-07-22 | 2001-02-09 | Hitachi Ltd | 半導体記憶装置 |
JP2001167574A (ja) * | 1999-12-08 | 2001-06-22 | Mitsubishi Electric Corp | 半導体記憶装置 |
JP2002334576A (ja) * | 2001-05-07 | 2002-11-22 | Samsung Electronics Co Ltd | 半導体メモリ装置及びそのリフレッシュ動作の制御方法 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR19990042331A (ko) | 1997-11-26 | 1999-06-15 | 구본준 | 디램의 멀티 뱅크 리프레쉬 회로 |
US6246619B1 (en) * | 2000-02-07 | 2001-06-12 | Vanguard International Semiconductor Corp. | Self-refresh test time reduction scheme |
US6650587B2 (en) * | 2001-11-19 | 2003-11-18 | Micron Technology, Inc. | Partial array self-refresh |
KR100535071B1 (ko) | 2002-11-07 | 2005-12-07 | 주식회사 하이닉스반도체 | 셀프 리프레쉬 장치 |
KR100474551B1 (ko) * | 2003-02-10 | 2005-03-10 | 주식회사 하이닉스반도체 | 셀프 리프레쉬 장치 및 방법 |
KR100611774B1 (ko) * | 2004-06-03 | 2006-08-10 | 주식회사 하이닉스반도체 | 반도체 기억 소자의 뱅크 베이스드 부분 어레이 셀프 리프레쉬 장치 및 방법 |
-
2004
- 2004-11-15 KR KR1020040093117A patent/KR100608370B1/ko active IP Right Grant
-
2005
- 2005-05-04 DE DE102005020894A patent/DE102005020894A1/de not_active Withdrawn
- 2005-05-06 JP JP2005134894A patent/JP2006147123A/ja active Pending
- 2005-05-09 TW TW094114972A patent/TWI268509B/zh not_active IP Right Cessation
- 2005-05-10 US US11/125,687 patent/US7149140B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001035152A (ja) * | 1999-07-22 | 2001-02-09 | Hitachi Ltd | 半導体記憶装置 |
JP2001167574A (ja) * | 1999-12-08 | 2001-06-22 | Mitsubishi Electric Corp | 半導体記憶装置 |
JP2002334576A (ja) * | 2001-05-07 | 2002-11-22 | Samsung Electronics Co Ltd | 半導体メモリ装置及びそのリフレッシュ動作の制御方法 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7486584B2 (en) | 2006-08-22 | 2009-02-03 | Elpida Memory, Inc. | Semiconductor memory device and refresh control method thereof |
EP2079126A1 (en) | 2008-01-14 | 2009-07-15 | Samsung SDI Co., Ltd. | Impact Resistant Battery Pack |
US7881109B2 (en) | 2008-12-23 | 2011-02-01 | Hynix Semiconductor Inc. | Refresh circuit of semiconductor memory apparatus |
Also Published As
Publication number | Publication date |
---|---|
TWI268509B (en) | 2006-12-11 |
DE102005020894A1 (de) | 2006-05-24 |
US20060104139A1 (en) | 2006-05-18 |
KR100608370B1 (ko) | 2006-08-08 |
TW200615954A (en) | 2006-05-16 |
KR20060053426A (ko) | 2006-05-22 |
US7149140B2 (en) | 2006-12-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP2006147123A (ja) | メモリ装置のリフレッシュ方法 | |
US8116161B2 (en) | System and method for refreshing a DRAM device | |
US7548468B2 (en) | Semiconductor memory and operation method for same | |
JP2010170596A (ja) | 半導体記憶装置 | |
US20110161578A1 (en) | Semiconductor memory device performing partial self refresh and memory system including same | |
JP2008084426A (ja) | 半導体メモリおよびシステム | |
JP2008090904A (ja) | 半導体記憶装置及びメモリシステム | |
JP2008084428A (ja) | 半導体メモリおよびシステム | |
US6292420B1 (en) | Method and device for automatically performing refresh operation in semiconductor memory device | |
US8750067B2 (en) | Semiconductor device having reset function | |
US7042774B2 (en) | Semiconductor memory device to supply stable high voltage during auto-refresh operation and method therefor | |
US7263021B2 (en) | Refresh circuit for use in semiconductor memory device and operation method thereof | |
US10878876B2 (en) | Apparatuses and methods for providing power for memory refresh operations | |
JP2006146992A (ja) | 半導体メモリ装置 | |
US7145814B2 (en) | RAS time control circuit and method for use in DRAM using external clock | |
US10818335B2 (en) | Memory storage apparatus and operating method with multiple modes for refresh operation | |
TWI582580B (zh) | 記憶體儲存裝置及其操作方法 | |
KR20090126976A (ko) | 자동 리프레쉬 제어회로 | |
KR20060084071A (ko) | 반도체 메모리에서의 리프레쉬 제어회로 및 그에 따른제어방법 | |
US7428179B2 (en) | Apparatus for controlling activation of semiconductor integrated circuit and controlling method of the same | |
JP2007280608A (ja) | 半導体記憶装置 | |
KR101020289B1 (ko) | 셀프리프레쉬 테스트회로 | |
JP2006048845A (ja) | セルフリフレッシュ制御回路 | |
KR100200718B1 (ko) | 다이내믹 메모리장치에서의 cbr 리프레쉬 제어방법 | |
JP4100403B2 (ja) | 半導体メモリ装置におけるリフレッシュ制御および内部電圧の生成 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20060612 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20081203 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20090303 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20090428 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20090727 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20090730 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20090826 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20091028 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100301 |
|
A911 | Transfer to examiner for re-examination before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20100330 |
|
A912 | Re-examination (zenchi) completed and case transferred to appeal board |
Free format text: JAPANESE INTERMEDIATE CODE: A912 Effective date: 20100604 |