KR20050030162A - 보호층 형성 공정 - Google Patents

보호층 형성 공정 Download PDF

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Publication number
KR20050030162A
KR20050030162A KR1020040076661A KR20040076661A KR20050030162A KR 20050030162 A KR20050030162 A KR 20050030162A KR 1020040076661 A KR1020040076661 A KR 1020040076661A KR 20040076661 A KR20040076661 A KR 20040076661A KR 20050030162 A KR20050030162 A KR 20050030162A
Authority
KR
South Korea
Prior art keywords
protective layer
fuse
deposited
forming process
interconnects
Prior art date
Application number
KR1020040076661A
Other languages
English (en)
Korean (ko)
Inventor
파이퍼올리버
달만제랄드
베버데틀레프
Original Assignee
인피네온 테크놀로지스 아게
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 인피네온 테크놀로지스 아게 filed Critical 인피네온 테크놀로지스 아게
Publication of KR20050030162A publication Critical patent/KR20050030162A/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • H01L23/5258—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive the change of state resulting from the use of an external beam, e.g. laser beam or ion beam
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
KR1020040076661A 2003-09-24 2004-09-23 보호층 형성 공정 KR20050030162A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10344502A DE10344502A1 (de) 2003-09-24 2003-09-24 Verfahren zum Aufbringen von Schutzschichten auf Fuse-Leitbahnen
DE10344502.1 2003-09-24

Publications (1)

Publication Number Publication Date
KR20050030162A true KR20050030162A (ko) 2005-03-29

Family

ID=34398942

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020040076661A KR20050030162A (ko) 2003-09-24 2004-09-23 보호층 형성 공정

Country Status (2)

Country Link
KR (1) KR20050030162A (de)
DE (1) DE10344502A1 (de)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6122650A (ja) * 1984-07-11 1986-01-31 Hitachi Ltd 欠陥救済方法および装置
US5025300A (en) * 1989-06-30 1991-06-18 At&T Bell Laboratories Integrated circuits having improved fusible links
US5879966A (en) * 1994-09-06 1999-03-09 Taiwan Semiconductor Manufacturing Company Ltd. Method of making an integrated circuit having an opening for a fuse
US5650355A (en) * 1995-03-30 1997-07-22 Texas Instruments Incorporated Process of making and process of trimming a fuse in a top level metal and in a step
US5538924A (en) * 1995-09-05 1996-07-23 Vanguard International Semiconductor Co. Method of forming a moisture guard ring for integrated circuit applications

Also Published As

Publication number Publication date
DE10344502A1 (de) 2005-05-04

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Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E601 Decision to refuse application