DE10344502A1 - Verfahren zum Aufbringen von Schutzschichten auf Fuse-Leitbahnen - Google Patents

Verfahren zum Aufbringen von Schutzschichten auf Fuse-Leitbahnen Download PDF

Info

Publication number
DE10344502A1
DE10344502A1 DE10344502A DE10344502A DE10344502A1 DE 10344502 A1 DE10344502 A1 DE 10344502A1 DE 10344502 A DE10344502 A DE 10344502A DE 10344502 A DE10344502 A DE 10344502A DE 10344502 A1 DE10344502 A1 DE 10344502A1
Authority
DE
Germany
Prior art keywords
carrying
etching process
strip conductors
semiconductor arrangement
protective layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
DE10344502A
Other languages
English (en)
Inventor
Oliver Pyper
Gerald Dallmann
Detlef Weber
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Priority to DE10344502A priority Critical patent/DE10344502A1/de
Priority to KR1020040076661A priority patent/KR20050030162A/ko
Publication of DE10344502A1 publication Critical patent/DE10344502A1/de
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • H01L23/5258—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive the change of state resulting from the use of an external beam, e.g. laser beam or ion beam
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

Die Erfindung betrifft ein Verfahren zum Aufbringen von Schutzschichten auf Fuse-Leitbahnen, wobei eine Halbleiteranordnung durch eine abschließende Passivierungsschicht abgedeckt wurde. Durch die Erfindung soll ein Verfahren zum Aufbringen von Schutzschichten auf Fuse-Leitbahnen angegeben werden, mit dem die Problematik der Korrosion beseitigt, und damit die Funktionsfähigkeit des Bauteiles gewährleistet wird. Erreicht wird das dadurch, dass nach dem Passivieren der Halbleiteranordnung ein erster zusätzlicher Lithographie/Ätz-Prozessschritt durchgeführt wird, wobei Kontakt-Pads und Fuse-Leitbahnen freigelegt werden, anschließend erfolgt ein erster zusätzlicher Abscheide-Prozessschritt, wobei eine weitere Schutzschicht (8) auf die Halbleiteranordnung aufgetragen wird, danach erfolgt ein zweiter weiterer Lithographie/Ätz-Prozessschritt, wobei die Kontakt-Pads belichtet und anschließend freigeätzt werden.
DE10344502A 2003-09-24 2003-09-24 Verfahren zum Aufbringen von Schutzschichten auf Fuse-Leitbahnen Ceased DE10344502A1 (de)

Priority Applications (2)

Application Number Priority Date Filing Date Title
DE10344502A DE10344502A1 (de) 2003-09-24 2003-09-24 Verfahren zum Aufbringen von Schutzschichten auf Fuse-Leitbahnen
KR1020040076661A KR20050030162A (ko) 2003-09-24 2004-09-23 보호층 형성 공정

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE10344502A DE10344502A1 (de) 2003-09-24 2003-09-24 Verfahren zum Aufbringen von Schutzschichten auf Fuse-Leitbahnen

Publications (1)

Publication Number Publication Date
DE10344502A1 true DE10344502A1 (de) 2005-05-04

Family

ID=34398942

Family Applications (1)

Application Number Title Priority Date Filing Date
DE10344502A Ceased DE10344502A1 (de) 2003-09-24 2003-09-24 Verfahren zum Aufbringen von Schutzschichten auf Fuse-Leitbahnen

Country Status (2)

Country Link
KR (1) KR20050030162A (de)
DE (1) DE10344502A1 (de)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4795720A (en) * 1984-07-11 1989-01-03 Hitachi, Ltd. Method for producing semiconductor devices and cutting fuses
US5025300A (en) * 1989-06-30 1991-06-18 At&T Bell Laboratories Integrated circuits having improved fusible links
US5538924A (en) * 1995-09-05 1996-07-23 Vanguard International Semiconductor Co. Method of forming a moisture guard ring for integrated circuit applications
US5965927A (en) * 1994-09-06 1999-10-12 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit having an opening for a fuse
US6331739B1 (en) * 1995-03-30 2001-12-18 Texas Instruments Incorporated Fuse in top level metal and in a step, process of making and process of trimming

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4795720A (en) * 1984-07-11 1989-01-03 Hitachi, Ltd. Method for producing semiconductor devices and cutting fuses
US5025300A (en) * 1989-06-30 1991-06-18 At&T Bell Laboratories Integrated circuits having improved fusible links
US5965927A (en) * 1994-09-06 1999-10-12 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit having an opening for a fuse
US6331739B1 (en) * 1995-03-30 2001-12-18 Texas Instruments Incorporated Fuse in top level metal and in a step, process of making and process of trimming
US5538924A (en) * 1995-09-05 1996-07-23 Vanguard International Semiconductor Co. Method of forming a moisture guard ring for integrated circuit applications

Also Published As

Publication number Publication date
KR20050030162A (ko) 2005-03-29

Similar Documents

Publication Publication Date Title
WO2002103755A3 (en) Semiconductor die including conductive columns
EP1333483A4 (de) Verfahren zum ätzen einer doppel-damaszin-struktur
WO2002017387A3 (en) Conductive material patterning methods
WO2006054024A3 (fr) Amincissement d'une plaquette semiconductrice
WO2005004195A3 (en) Method and apparatus for packaging integrated circuit devices
WO2004111659A3 (en) Methods and apparatus for packaging integrated circuit devices
TW200509740A (en) Process for removing an organic layer during fabrication of an organic electronic device and the organic electronic device formed by the process
TW200739811A (en) Interconnect structure of an integrated circuit, damascene structure, semiconductor structure and fabrication methods thereof
WO2006082199A3 (fr) Procédé de placement d'un ensemble électronique sur un substrat et dispositif de placement d'un tel ensemble
WO2004095515A3 (en) Methods for contracting conducting layers overlying magnetoelectronic elements of mram devices
TW373256B (en) A semiconductor device having discontinuous insulating regions and the manufacturing method thereof
TW200705568A (en) Method of forming an interlayer dielectric
WO2004077548A3 (de) Verbindungstechnik für leistungshalbleiter
TW200623948A (en) Manufacturing method for organic electronic device
MX2007003615A (es) Circuito integrado y metodo de fabricacion.
WO2001093328A3 (en) Lead frame laminate and method for manufacturing semiconductor parts
WO2003023865A1 (fr) Dispositif a semi-conducteurs et son procede de fabrication
TW200721372A (en) Method for forming narrow structures in a semiconductor device
WO2005079366A3 (en) Complimentary nitride transistors vertical and common drain
TW200514177A (en) Method of forming a bond pad on an I/C chip and resulting structure
WO2004109774A3 (en) Selective reference plane bridge(s) on folded package
TW200618102A (en) Semiconductor device with composite etch stop layer and fabrication method thereof
TW200633061A (en) Method for etching dielectric material in semiconductor device
TW346664B (en) Mixed-mode IC separated spacer structure and process for producing the same
DE10344502A1 (de) Verfahren zum Aufbringen von Schutzschichten auf Fuse-Leitbahnen

Legal Events

Date Code Title Description
ON Later submitted papers
OP8 Request for examination as to paragraph 44 patent law
8131 Rejection