DE10344502A1 - Verfahren zum Aufbringen von Schutzschichten auf Fuse-Leitbahnen - Google Patents
Verfahren zum Aufbringen von Schutzschichten auf Fuse-Leitbahnen Download PDFInfo
- Publication number
- DE10344502A1 DE10344502A1 DE10344502A DE10344502A DE10344502A1 DE 10344502 A1 DE10344502 A1 DE 10344502A1 DE 10344502 A DE10344502 A DE 10344502A DE 10344502 A DE10344502 A DE 10344502A DE 10344502 A1 DE10344502 A1 DE 10344502A1
- Authority
- DE
- Germany
- Prior art keywords
- carrying
- etching process
- strip conductors
- semiconductor arrangement
- protective layers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
- H01L23/5258—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive the change of state resulting from the use of an external beam, e.g. laser beam or ion beam
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Die Erfindung betrifft ein Verfahren zum Aufbringen von Schutzschichten auf Fuse-Leitbahnen, wobei eine Halbleiteranordnung durch eine abschließende Passivierungsschicht abgedeckt wurde. Durch die Erfindung soll ein Verfahren zum Aufbringen von Schutzschichten auf Fuse-Leitbahnen angegeben werden, mit dem die Problematik der Korrosion beseitigt, und damit die Funktionsfähigkeit des Bauteiles gewährleistet wird. Erreicht wird das dadurch, dass nach dem Passivieren der Halbleiteranordnung ein erster zusätzlicher Lithographie/Ätz-Prozessschritt durchgeführt wird, wobei Kontakt-Pads und Fuse-Leitbahnen freigelegt werden, anschließend erfolgt ein erster zusätzlicher Abscheide-Prozessschritt, wobei eine weitere Schutzschicht (8) auf die Halbleiteranordnung aufgetragen wird, danach erfolgt ein zweiter weiterer Lithographie/Ätz-Prozessschritt, wobei die Kontakt-Pads belichtet und anschließend freigeätzt werden.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10344502A DE10344502A1 (de) | 2003-09-24 | 2003-09-24 | Verfahren zum Aufbringen von Schutzschichten auf Fuse-Leitbahnen |
KR1020040076661A KR20050030162A (ko) | 2003-09-24 | 2004-09-23 | 보호층 형성 공정 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10344502A DE10344502A1 (de) | 2003-09-24 | 2003-09-24 | Verfahren zum Aufbringen von Schutzschichten auf Fuse-Leitbahnen |
Publications (1)
Publication Number | Publication Date |
---|---|
DE10344502A1 true DE10344502A1 (de) | 2005-05-04 |
Family
ID=34398942
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE10344502A Ceased DE10344502A1 (de) | 2003-09-24 | 2003-09-24 | Verfahren zum Aufbringen von Schutzschichten auf Fuse-Leitbahnen |
Country Status (2)
Country | Link |
---|---|
KR (1) | KR20050030162A (de) |
DE (1) | DE10344502A1 (de) |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4795720A (en) * | 1984-07-11 | 1989-01-03 | Hitachi, Ltd. | Method for producing semiconductor devices and cutting fuses |
US5025300A (en) * | 1989-06-30 | 1991-06-18 | At&T Bell Laboratories | Integrated circuits having improved fusible links |
US5538924A (en) * | 1995-09-05 | 1996-07-23 | Vanguard International Semiconductor Co. | Method of forming a moisture guard ring for integrated circuit applications |
US5965927A (en) * | 1994-09-06 | 1999-10-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit having an opening for a fuse |
US6331739B1 (en) * | 1995-03-30 | 2001-12-18 | Texas Instruments Incorporated | Fuse in top level metal and in a step, process of making and process of trimming |
-
2003
- 2003-09-24 DE DE10344502A patent/DE10344502A1/de not_active Ceased
-
2004
- 2004-09-23 KR KR1020040076661A patent/KR20050030162A/ko not_active Application Discontinuation
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4795720A (en) * | 1984-07-11 | 1989-01-03 | Hitachi, Ltd. | Method for producing semiconductor devices and cutting fuses |
US5025300A (en) * | 1989-06-30 | 1991-06-18 | At&T Bell Laboratories | Integrated circuits having improved fusible links |
US5965927A (en) * | 1994-09-06 | 1999-10-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit having an opening for a fuse |
US6331739B1 (en) * | 1995-03-30 | 2001-12-18 | Texas Instruments Incorporated | Fuse in top level metal and in a step, process of making and process of trimming |
US5538924A (en) * | 1995-09-05 | 1996-07-23 | Vanguard International Semiconductor Co. | Method of forming a moisture guard ring for integrated circuit applications |
Also Published As
Publication number | Publication date |
---|---|
KR20050030162A (ko) | 2005-03-29 |
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DE10344502A1 (de) | Verfahren zum Aufbringen von Schutzschichten auf Fuse-Leitbahnen |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
ON | Later submitted papers | ||
OP8 | Request for examination as to paragraph 44 patent law | ||
8131 | Rejection |