KR100475136B1 - 반도체 소자의 콘택 영역 형성 방법 - Google Patents
반도체 소자의 콘택 영역 형성 방법 Download PDFInfo
- Publication number
- KR100475136B1 KR100475136B1 KR10-2000-0072929A KR20000072929A KR100475136B1 KR 100475136 B1 KR100475136 B1 KR 100475136B1 KR 20000072929 A KR20000072929 A KR 20000072929A KR 100475136 B1 KR100475136 B1 KR 100475136B1
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- South Korea
- Prior art keywords
- film
- forming
- metal film
- terminal
- barc
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
- H01L21/0276—Photolithographic processes using an anti-reflective coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (2)
- 기판상의 일정영역에 리페어 단자를 형성하는 단계;상기 리페어 단자를 포함한 기판의 전면에 층간 절연막을 형성하는 단계;상기 층간 절연막상에 금속막을 형성하는 단계;상기 금속막상에 베리어 금속막을 형성하는 단계;상기 베리어 금속막상에 BARC막을 형성하는 단계;상기 BARC막, 베리어 금속막, 금속막을 선택적으로 제거하여 패드 단자를 형성하는 단계;상기 BARC막 및 베리어 금속막을 제거하는 단계;상기 패드 단자를 포함한 기판의 전면에 평탄화막을 형성하는 단계;상기 패드 단자의 표면이 소정부분 노출되도록 상기 평탄화막을 선택적으로 제거하여 콘택홀을 형성하는 단계를 포함하여 형성함을 특징으로 하는 반도체 소자의 콘택 영역 형성 방법.
- 제 1 항에 있어서, 상기 베리어 금속막은 상기 금속막에 UVAS 처리를 진행하여 O3과 반응시키어 형성하는 것을 특징으로 하는 반도체 소자의 콘택 영역 형성 방법.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2000-0072929A KR100475136B1 (ko) | 2000-12-04 | 2000-12-04 | 반도체 소자의 콘택 영역 형성 방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2000-0072929A KR100475136B1 (ko) | 2000-12-04 | 2000-12-04 | 반도체 소자의 콘택 영역 형성 방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20020043805A KR20020043805A (ko) | 2002-06-12 |
KR100475136B1 true KR100475136B1 (ko) | 2005-03-08 |
Family
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Application Number | Title | Priority Date | Filing Date |
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KR10-2000-0072929A KR100475136B1 (ko) | 2000-12-04 | 2000-12-04 | 반도체 소자의 콘택 영역 형성 방법 |
Country Status (1)
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KR (1) | KR100475136B1 (ko) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100805695B1 (ko) * | 2005-08-17 | 2008-02-21 | 주식회사 하이닉스반도체 | 메탈퓨즈를 구비한 반도체소자의 제조 방법 |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100881411B1 (ko) * | 2002-10-15 | 2009-02-05 | 매그나칩 반도체 유한회사 | Mdl 소자의 제조방법 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09153552A (ja) * | 1995-11-29 | 1997-06-10 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JPH11214389A (ja) * | 1998-01-23 | 1999-08-06 | Toshiba Corp | 半導体装置の製造方法 |
US5985765A (en) * | 1998-05-11 | 1999-11-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for reducing bonding pad loss using a capping layer when etching bonding pad passivation openings |
KR19990088152A (ko) * | 1998-05-11 | 1999-12-27 | 비센트 비.인그라시아 | 집적회로형성방법 |
KR20000020312A (ko) * | 1998-09-19 | 2000-04-15 | 김영환 | 반도체 소자 제조방법 |
-
2000
- 2000-12-04 KR KR10-2000-0072929A patent/KR100475136B1/ko active IP Right Grant
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09153552A (ja) * | 1995-11-29 | 1997-06-10 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JPH11214389A (ja) * | 1998-01-23 | 1999-08-06 | Toshiba Corp | 半導体装置の製造方法 |
US5985765A (en) * | 1998-05-11 | 1999-11-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for reducing bonding pad loss using a capping layer when etching bonding pad passivation openings |
KR19990088152A (ko) * | 1998-05-11 | 1999-12-27 | 비센트 비.인그라시아 | 집적회로형성방법 |
KR20000020312A (ko) * | 1998-09-19 | 2000-04-15 | 김영환 | 반도체 소자 제조방법 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100805695B1 (ko) * | 2005-08-17 | 2008-02-21 | 주식회사 하이닉스반도체 | 메탈퓨즈를 구비한 반도체소자의 제조 방법 |
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Publication number | Publication date |
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KR20020043805A (ko) | 2002-06-12 |
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