KR20040057580A - 듀얼 다마신 구조를 갖는 미세 패턴 형성 방법 - Google Patents
듀얼 다마신 구조를 갖는 미세 패턴 형성 방법 Download PDFInfo
- Publication number
- KR20040057580A KR20040057580A KR1020020084341A KR20020084341A KR20040057580A KR 20040057580 A KR20040057580 A KR 20040057580A KR 1020020084341 A KR1020020084341 A KR 1020020084341A KR 20020084341 A KR20020084341 A KR 20020084341A KR 20040057580 A KR20040057580 A KR 20040057580A
- Authority
- KR
- South Korea
- Prior art keywords
- pattern
- photoresist
- forming
- interlayer insulating
- photoresist pattern
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 47
- 230000009977 dual effect Effects 0.000 title claims abstract description 16
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 55
- 239000011229 interlayer Substances 0.000 claims abstract description 28
- 230000008569 process Effects 0.000 claims abstract description 26
- 238000004017 vitrification Methods 0.000 claims abstract description 20
- 239000010410 layer Substances 0.000 claims abstract description 16
- 125000006850 spacer group Chemical group 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 239000004065 semiconductor Substances 0.000 claims description 9
- 239000002253 acid Substances 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 5
- 238000011161 development Methods 0.000 claims description 3
- 238000004891 communication Methods 0.000 claims description 2
- 238000000059 patterning Methods 0.000 abstract 2
- 239000010408 film Substances 0.000 description 49
- 239000010949 copper Substances 0.000 description 23
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 19
- 229910052802 copper Inorganic materials 0.000 description 18
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000001459 lithography Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 230000018109 developmental process Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 230000007261 regionalization Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- OCXZUOIMVATIKY-UHFFFAOYSA-N [Cu].C[Si](C)(C)C=C Chemical compound [Cu].C[Si](C)(C)C=C OCXZUOIMVATIKY-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- -1 and generally Chemical compound 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- HZXGNBMOOYOYIS-PAMPIZDHSA-L copper;(z)-1,1,1,5,5,5-hexafluoro-4-oxopent-2-en-2-olate Chemical compound [Cu+2].FC(F)(F)C(/[O-])=C/C(=O)C(F)(F)F.FC(F)(F)C(/[O-])=C/C(=O)C(F)(F)F HZXGNBMOOYOYIS-PAMPIZDHSA-L 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000002902 organometallic compounds Chemical class 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
- H01L21/0275—Photolithographic processes using lasers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Optics & Photonics (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (6)
- 하부 도전 패턴이 형성된 반도체 기판을 제공하는 단계;상기 반도체 기판상에 제 1 및 제 2 층간 절연막을 순차적으로 형성하는 단계;상기 제 2 층간 절연막상에 1 유리화 온도를 갖는 제 1 감광막과 제 2 유리화 온도를 갖는 제 2 감광막을 형성하는 단계;노광 및 현상공정에 의해 상기 제 1 및 제 2 감광막을 제거하여 제 1 감광막 패턴을 형성하는 단계;오픈 프레임 노광 공정을 실시하여 상기 제 1 감광막 패턴의 최외각쪽에만 산이 생성되도록 하는 단계;리플로우 공정을 실시하여 상기 감광막 패턴의 측벽에 오버행이 없는 감광막 스페이서를 형성하는 단계;상기 제 1 감광막 패턴을 마스크로한 식각 공정에 의해 상기 제 1 및 제 2 층간 절연막을 제거하여 비아홀을 형성하는 단계;상기 감광막 패턴 및 제 감광막 스페이서를 제거하고 제 2 감광막 패턴을 형성하는 단계:상기 감광막 패턴을 마스크로 하여 노출된 상기 제 2 층간 절연막을 제거하여 상기 비아홀과 연통되는 트랜치를 형성하는 단계를 포함하여 이루어 진 것을 특징으로 하는 듀얼 다마신 구조를 갖는 미세 패턴 형성 방법.
- 제 1 항에 있어서,상기 제 1 유리화 온도는 상기 제 2 유리화 온도 보다 낮은 것을 특징으로 하는 듀얼 다마신 구조를 갖는 미세 패턴 형성 방법.
- 제 1 항에 있어서,상기 오픈 프레임 노광 공정시의 노광 에너지는 상기 제 1 감광막 패턴 형성시의 노강 에너지 보다 작은 것을 특징으로 하는 듀얼 다마신 구조를 갖는 미세 패턴 형성 방법.
- 제 1 항에 있어서,상기 노광 공정은 에시머 레이져를 이용하는 것을 특징으로 하는 듀얼 다마신 구조를 갖는 미세 패턴 형성 방법.
- 제 1 항에 있어서,상기 제 2 감광막 패턴 형성전에 상기 제 2 층간 절연막의 상부 전체 또는 일부에 반사 방지막을 형성하는 단계를 더 포함하는 것을 특징으로 하는 듀얼 다마신 구조를 갖는 미세 패턴 형성 방법.
- 제 1 항에 있어서,상기 제 1 및 제 2 층간 절연막 각각의 유전 상수는 2.0 내지 2.7인 것을 특징으로 하는 듀얼 다마신 구조를 갖는 미세 패턴 형성 방법.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2002-0084341A KR100471576B1 (ko) | 2002-12-26 | 2002-12-26 | 듀얼 다마신 구조를 갖는 미세 패턴 형성 방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2002-0084341A KR100471576B1 (ko) | 2002-12-26 | 2002-12-26 | 듀얼 다마신 구조를 갖는 미세 패턴 형성 방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20040057580A true KR20040057580A (ko) | 2004-07-02 |
KR100471576B1 KR100471576B1 (ko) | 2005-03-10 |
Family
ID=37350144
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR10-2002-0084341A KR100471576B1 (ko) | 2002-12-26 | 2002-12-26 | 듀얼 다마신 구조를 갖는 미세 패턴 형성 방법 |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR100471576B1 (ko) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100715600B1 (ko) * | 2005-12-28 | 2007-05-10 | 동부일렉트로닉스 주식회사 | 반도체소자의 미세패턴 형성방법 |
US9379003B2 (en) | 2012-10-25 | 2016-06-28 | Samsung Electronics Co., Ltd. | Semiconductor structures and methods of manufacturing the same |
US9613862B2 (en) | 2015-09-02 | 2017-04-04 | International Business Machines Corporation | Chamferless via structures |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100791694B1 (ko) * | 2006-11-24 | 2008-01-03 | 동부일렉트로닉스 주식회사 | 듀얼 다마신을 이용한 금속 배선의 제조 방법 |
-
2002
- 2002-12-26 KR KR10-2002-0084341A patent/KR100471576B1/ko active IP Right Grant
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100715600B1 (ko) * | 2005-12-28 | 2007-05-10 | 동부일렉트로닉스 주식회사 | 반도체소자의 미세패턴 형성방법 |
US9379003B2 (en) | 2012-10-25 | 2016-06-28 | Samsung Electronics Co., Ltd. | Semiconductor structures and methods of manufacturing the same |
US9754817B2 (en) | 2012-10-25 | 2017-09-05 | Samsung Electronics Co., Ltd. | Semiconductor structures having an insulative island structure |
US9613862B2 (en) | 2015-09-02 | 2017-04-04 | International Business Machines Corporation | Chamferless via structures |
US10032668B2 (en) | 2015-09-02 | 2018-07-24 | International Business Machines Corporation | Chamferless via structures |
US10388565B2 (en) | 2015-09-02 | 2019-08-20 | International Business Machines Corporation | Chamferless via structures |
US10903118B2 (en) | 2015-09-02 | 2021-01-26 | International Business Machines Corporation | Chamferless via structures |
US10937694B2 (en) | 2015-09-02 | 2021-03-02 | International Business Machines Corporation | Chamferless via structures |
US10957588B2 (en) | 2015-09-02 | 2021-03-23 | International Business Machines Corporation | Chamferless via structures |
Also Published As
Publication number | Publication date |
---|---|
KR100471576B1 (ko) | 2005-03-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100494955B1 (ko) | 유동성희생산화물을이용하는이중다마신법을사용한다층동일평면금속/절연체막형성방법 | |
KR20040057582A (ko) | 듀얼 다마신 구조를 갖는 미세 패턴 형성 방법 | |
JP7362268B2 (ja) | 多色自己整合接点の選択的エッチング | |
JP2011204997A (ja) | 半導体装置の製造方法及び半導体装置 | |
KR100471576B1 (ko) | 듀얼 다마신 구조를 갖는 미세 패턴 형성 방법 | |
KR100422356B1 (ko) | 반도체소자의 콘택 형성방법 | |
KR100324023B1 (ko) | 반도체소자의제조방법 | |
KR100315039B1 (ko) | 반도체 소자의 금속배선 형성방법 | |
KR100257069B1 (ko) | 반도체소자의 패터닝 방법 | |
KR20040057581A (ko) | 듀얼 다마신 구조를 갖는 미세 패턴 형성 방법 | |
KR20040057517A (ko) | 듀얼 다마신 패턴 형성 방법 | |
KR100324021B1 (ko) | 반도체소자의제조방법 | |
KR0139575B1 (ko) | 반도체 소자 제조방법 | |
KR100226753B1 (ko) | 반도체 소자의 금속배선 형성방법 | |
KR100519644B1 (ko) | 반도체 소자의 게이트 형성 방법 | |
KR100539446B1 (ko) | 반도체 소자의 듀얼 다마신 패턴 형성방법 | |
KR100539447B1 (ko) | 반도체 소자의 금속 배선 형성방법 | |
KR100379530B1 (ko) | 반도체 소자의 듀얼 다마신 형성방법 | |
KR101005738B1 (ko) | 반도체 소자의 듀얼 다마신 패턴 형성방법 | |
KR100917099B1 (ko) | 듀얼 다마신 패턴 형성 방법 | |
KR20010061788A (ko) | 플러그 형성 후에 층간 절연막을 증착하는 다층 금속배선의 형성 방법 | |
JP5699803B2 (ja) | 半導体装置の製造方法 | |
KR100406581B1 (ko) | 반도체 소자의 제조방법 | |
KR100617044B1 (ko) | 반도체 소자의 금속배선 형성방법 | |
KR100275127B1 (ko) | 반도체 소자의 다층 금속 배선 평탄화방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
N231 | Notification of change of applicant | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20130122 Year of fee payment: 9 |
|
FPAY | Annual fee payment |
Payment date: 20140116 Year of fee payment: 10 |
|
FPAY | Annual fee payment |
Payment date: 20150116 Year of fee payment: 11 |
|
FPAY | Annual fee payment |
Payment date: 20160119 Year of fee payment: 12 |
|
FPAY | Annual fee payment |
Payment date: 20170117 Year of fee payment: 13 |
|
FPAY | Annual fee payment |
Payment date: 20180116 Year of fee payment: 14 |
|
FPAY | Annual fee payment |
Payment date: 20190117 Year of fee payment: 15 |
|
FPAY | Annual fee payment |
Payment date: 20200116 Year of fee payment: 16 |