KR20040057580A - Method of forming a micro pattern having a dual damascene - Google Patents
Method of forming a micro pattern having a dual damascene Download PDFInfo
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- KR20040057580A KR20040057580A KR1020020084341A KR20020084341A KR20040057580A KR 20040057580 A KR20040057580 A KR 20040057580A KR 1020020084341 A KR1020020084341 A KR 1020020084341A KR 20020084341 A KR20020084341 A KR 20020084341A KR 20040057580 A KR20040057580 A KR 20040057580A
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- 238000000034 method Methods 0.000 title claims abstract description 47
- 230000009977 dual effect Effects 0.000 title claims abstract description 16
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 55
- 239000011229 interlayer Substances 0.000 claims abstract description 28
- 230000008569 process Effects 0.000 claims abstract description 26
- 238000004017 vitrification Methods 0.000 claims abstract description 20
- 239000010410 layer Substances 0.000 claims abstract description 16
- 125000006850 spacer group Chemical group 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 239000004065 semiconductor Substances 0.000 claims description 9
- 239000002253 acid Substances 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 5
- 238000011161 development Methods 0.000 claims description 3
- 238000004891 communication Methods 0.000 claims description 2
- 238000000059 patterning Methods 0.000 abstract 2
- 239000010408 film Substances 0.000 description 49
- 239000010949 copper Substances 0.000 description 23
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 19
- 229910052802 copper Inorganic materials 0.000 description 18
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000001459 lithography Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 230000018109 developmental process Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 230000007261 regionalization Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- OCXZUOIMVATIKY-UHFFFAOYSA-N [Cu].C[Si](C)(C)C=C Chemical compound [Cu].C[Si](C)(C)C=C OCXZUOIMVATIKY-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- -1 and generally Chemical compound 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- HZXGNBMOOYOYIS-PAMPIZDHSA-L copper;(z)-1,1,1,5,5,5-hexafluoro-4-oxopent-2-en-2-olate Chemical compound [Cu+2].FC(F)(F)C(/[O-])=C/C(=O)C(F)(F)F.FC(F)(F)C(/[O-])=C/C(=O)C(F)(F)F HZXGNBMOOYOYIS-PAMPIZDHSA-L 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000002902 organometallic compounds Chemical class 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
- H01L21/0275—Photolithographic processes using lasers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
Description
본 발명은 듀얼 다마신 구조를 갖는 미세 패턴 형성 방법에 관한 것으로, 특히 오버행의 발생을 억제할 수 있는 듀얼 다마신 구조를 갖는 미세 패턴 형성 방법에 관한 것이다.The present invention relates to a fine pattern formation method having a dual damascene structure, and more particularly to a fine pattern formation method having a dual damascene structure capable of suppressing the occurrence of overhang.
일반적으로, 반도체소자의 고집적화와 더불어 고성능화가 지속적으로 진행되어 왔고 이에 추가하여 반도체소자의 고속화도 진행되어 왔다. 고성능 로직소자의 경우, 게이트 산화막의 두께 감소와 게이트전극의 길이 축소가 동작속도의 개선에 영향을 주지만, 배선 저항과 층간 절연막의 커패시턴스에 의한 RC지연이 동작속도의 악화에 더 많은 영향을 주고 있는 실정이다.In general, high performance has been continuously progressed along with high integration of semiconductor devices, and in addition, high speed semiconductor devices have been advanced. In the case of high-performance logic devices, the reduction of the thickness of the gate oxide film and the reduction of the length of the gate electrode affect the improvement of the operating speed, but the RC delay caused by the wiring resistance and the capacitance of the interlayer insulating film has more influence on the deterioration of the operating speed. It is true.
이러한 RC지연을 개선하기 위하여 여러 가지 방법들이 제안되어 왔고 그 중에서 구리(Cu)와 저유전 막질을 도입하는 방법이 현재 추진중에 있다. 구리(Cu)는 비저항 2.62Ωμ㎝의 알루미늄에 비하여 약 35%의 낮은 1.69Ωμ㎝의 비저항을 갖고, 또한 재료 가격이 값싸고, 일렉트로마이그레이션(electromigration) 수명도 길어서 차세대 배선재료로서 많은 업체에서 채용하고 있다.In order to improve the RC delay, various methods have been proposed. Among them, a method of introducing copper (Cu) and low dielectric film quality is currently being promoted. Copper has a specific resistance of 1.69Ωμcm, which is about 35% lower than that of aluminum having a specific resistance of 2.62Ωμcm, low cost of materials, and long electromigration life. have.
특히 우수한 물성의 구리 박막을 얻기 위해 화학기상증착법(CVD: chemical vapor deposition)의 적용이 검토되고 있다. 화학기상증착법으로 구리 박막을 형성하기 위하여 구리원으로 (hfac) Cu (VTMS)[1, 1, 1, 5, 5, 5 - hexafluoro-2,4-pent anedionato(vinyltrimethylsilane)copper(I):C10H13O2CuF6Si]와Cu(hfac)2[bis(1,1,1,5,5,5-hexafluoro-2,4-pentanedionato)copper(II):C10H2O4CuF12]로 대표되는 β-디케토니트(β-diketonate)계 Cu(I),Cu(II) 유기금속화합물을 사용하고 있다.In particular, in order to obtain a copper thin film having excellent physical properties, application of chemical vapor deposition (CVD) has been studied. (Hfac) Cu (VTMS) [1,1,1,5,5,5-hexafluoro-2,4-pent anedionato (vinyltrimethylsilane) copper (I): C10H13O2CuF6Si as a copper source to form a copper thin film by chemical vapor deposition Β-diketonate represented by Cu (hfac) 2 [bis (1,1,1,5,5,5-hexafluoro-2,4-pentanedionato) copper (II): C10H2O4CuF12] Cu (I) and Cu (II) organometallic compounds are used.
이러한 구리를 이용한 반도체 집적 회로 소자의 금속 배선을 형성하기 위해 듀얼 다마신 공정이 이용되고 있는데, 일반적으로 비아 콘택홀과 배선영역을 구현하기 위한 듀얼 다마신 패턴 공정 후 증착 공정을 통해 구리를 채워 넣는다. 이후, 구리를 화학적 기계적 연마법(CMP)으로 편탄화 하면 구리 배선이 완성된다. 일반적인 다마신 공정은 비아리쏘그래피, 비아식각과 스트립, 트랜치 리쏘그래피, 트랜치 식각과 스트립 순으로 형성되거나 트랜치 리쏘그래피, 트랜치 식각과 스트립, 비아 리쏘그래피, 비아식각과 스트립의 순서로 형성된다. 최신의 노광 장비와 RET 등의 방법을 우선 적용하지 않을 경우 디자인 룰이 더욱 감소 할때 비아홀을 구현하는 것이 공정 마진 부족 또는 구현 자체가 어려워 진다A dual damascene process is used to form a metal interconnection of a semiconductor integrated circuit device using copper, and generally, copper is filled through a deposition process after a dual damascene pattern process to realize a via contact hole and a wiring region. . Subsequently, the copper wiring is completed when the copper is carbonized by chemical mechanical polishing (CMP). Typical damascene processes are via lithography, via etch and strip, trench lithography, trench etch and strip, or trench lithography, trench etch and strip, via lithography, via etch and strip. If the latest exposure equipment and the RET method are not applied first, the implementation of via holes when the design rule is further reduced makes process margins short or difficult to implement itself.
종래 기술에 따른 듀얼 다마신 구조를 갖는 미세 패턴 형성 방법을 도 1을 참조하여 설명하기로 한다.A fine pattern forming method having a dual damascene structure according to the prior art will be described with reference to FIG. 1.
반도체 기판(도시 안됨)상에 형성된 제 1 층간 절연막(1)내에 구리 패턴(20)이 형성된다. 구리 패턴(20)을 포함한 전체 구조 상부에 제 2 및 제 3 층간 절연막(3 및 4)이 형성되고 그 상부에 감광막(5)을 도포한후 노광 및 현상 공정을 통해 감광막 패턴을 형성하게 되는데, 이때, 감광막의 도포 후 리플로우 공정 적용시 감광막의 일부가 플로우되어 감광막 패턴의 측벽에 오버행(A)이 발생되어 DICD(Devoloped Inspection Critical Dimension)2가 줄어들게 된다. 이러한 상태에서 식각 공정을 진행하면 수직한 비아홀을 구현할 수 없게 되어 배선후 최종 소자에서 기대하는 특성이 열화될 수 있다.A copper pattern 20 is formed in the first interlayer insulating film 1 formed on the semiconductor substrate (not shown). The second and third interlayer insulating films 3 and 4 are formed on the entire structure including the copper pattern 20, and the photoresist film 5 is coated on the photoresist layer, and then the photoresist pattern is formed through an exposure and development process. At this time, when the reflow process is applied after the application of the photoresist film, a part of the photoresist film flows to generate an overhang A on the sidewall of the photoresist pattern, thereby reducing DICD (Devoloped Inspection Critical Dimension) 2. If the etching process is performed in this state, vertical via holes may not be realized, and thus, characteristics expected in the final device after wiring may be degraded.
따라서, 본 발명은 유리화 온도가 상이한 감광막을 도포하여 리플로우 공정 적용시 오버행이 발생되지 않도록 하여 상기한 단점을 해소 할 수 있는 듀얼 다마신 패턴 구조를 갖는 미세 패턴 형성 방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method of forming a fine pattern having a dual damascene pattern structure which can solve the above-mentioned disadvantages by applying a photosensitive film having a different vitrification temperature so that an overhang does not occur when a reflow process is applied. .
도 1 은 종래 기술에 따른 듀얼 다마신 구조를 갖는 미세 패턴 형성 방법을 설명하기 위한 단면도이다.1 is a cross-sectional view illustrating a method for forming a fine pattern having a dual damascene structure according to the prior art.
도 2a 내지 도 2i 는 본 발명에 다른 듀얼 다마신 구조를 갖는 미세 패턴 형성 방법을 설명하기 위한 단면도이다.2A to 2I are cross-sectional views illustrating a method for forming a fine pattern having a dual damascene structure according to the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
1: 제 1 층간 절연막 2: 구리1: first interlayer insulating film 2: copper
3 및 4: 제 2 및 제 3 층간 절연막3 and 4: second and third interlayer insulating films
50: 제 1 유리화 온도를 갖는 감광막50: photosensitive film having first vitrification temperature
5: 제 2 유리화 온도를 갖는 감광막5: photosensitive film having a second vitrification temperature
5a: 감광막 스페이서5a: photoresist spacer
6: 감광막6: photosensitive film
상술한 목적을 달성하기 위한 본 발명에 따른 듀얼 다마신 구조를 갖는 미세 패턴 형성 방법은 하부 도전 패턴이 형성된 반도체 기판을 제공하는 단계;According to an aspect of the present invention, there is provided a method of forming a fine pattern having a dual damascene structure, including: providing a semiconductor substrate on which a lower conductive pattern is formed;
상기 반도체 기판상에 제 1 및 제 2 층간 절연막을 순차적으로 형성하는 단계;Sequentially forming a first and a second interlayer insulating film on the semiconductor substrate;
상기 제 2 층간 절연막상에 1 유리화 온도를 갖는 제 1 감광막과 제 2 유리화 온도를 갖는 제 2 감광막을 형성하는 단계;Forming a first photosensitive film having a first vitrification temperature and a second photosensitive film having a second vitrification temperature on the second interlayer insulating film;
노광 및 현상공정에 의해 상기 제 1 및 제 2 감광막을 제거하여 제 1 감광막 패턴을 형성하는 단계;Removing the first and second photoresist layers by an exposure and development process to form a first photoresist pattern;
오픈 프레임 노광 공정을 실시하여 상기 제 1 감광막 패턴의 최외각쪽에만 산이 생성되도록 하는 단계;Performing an open frame exposure process to generate acid only at the outermost side of the first photoresist pattern;
리플로우 공정을 실시하여 상기 감광막 패턴의 측벽에 오버행이 없는 감광막 스페이서를 형성하는 단계;Performing a reflow process to form a photoresist spacer having no overhang on sidewalls of the photoresist pattern;
상기 제 1 감광막 패턴을 마스크로한 식각 공정에 의해 상기 제 1 및 제 2 층간 절연막을 제거하여 비아홀을 형성하는 단계;Forming a via hole by removing the first and second interlayer insulating layers by an etching process using the first photoresist pattern as a mask;
상기 감광막 패턴 및 제 감광막 스페이서를 제거하고 제 2 감광막 패턴을 형성하는 단계:Removing the photoresist pattern and the photoresist spacer and forming a second photoresist pattern;
상기 감광막 패턴을 마스크로 하여 노출된 상기 제 2 층간 절연막을 제거하여 상기 비아홀과 연통되는 트랜치를 형성하는 단계를 포함하여 이루어 진 것을 특징으로 한다.And forming a trench in communication with the via hole by removing the exposed second interlayer insulating layer using the photoresist pattern as a mask.
이하, 첨부된 도면을 참조하여 본 발명의 실시예를 상세히 설명하기로 한다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2i 는 본 발명에 따른 다마신 구조를 갖는 미세 패턴 형성 방법을 설명하기 위한 단면도이다.2A to 2I are cross-sectional views illustrating a method of forming a fine pattern having a damascene structure according to the present invention.
도 2a를 참조하면, 반도체 기판(도시 안됨)상에 저유전 물질인 제 1 층간 절연막(1)을 플라즈마 화학 기상 증착법을 이용하여 형성한 후 콘택을 형성한다. 콘택을 포함한 전체 구조 상부에 구리(2)를 증착한다.Referring to FIG. 2A, a first interlayer insulating film 1, which is a low dielectric material, is formed on a semiconductor substrate (not shown) by using a plasma chemical vapor deposition method to form a contact. Copper (2) is deposited over the entire structure, including the contacts.
도 2b 를 참조하면, 제 1 층간 절연막(1)이 노출될 때까지 화학적 기계적 연마법을 이용한 평탄화 공정을 실시하여 구리 패턴(20)을 형성한다.Referring to FIG. 2B, the copper pattern 20 is formed by performing a planarization process using chemical mechanical polishing until the first interlayer insulating film 1 is exposed.
도 2c를 참조하면, 구리 패턴(20)을 포함한 전체 구조 상부에 제 2 층간 절연막(3), 제 3 층간 절연막(4), 제 1 유리화 온도를 갖는 감광막(50) 및 제 2 유리화 온도를 갖는 감광막(5)을 순차적으로 형성한다. 제 2 및 제 3 층간 절연막(3 및 4)은 화학 기상 증착법으로 형성되며 유전 상수가 작은 물질을 사용하는 것이 바람직한데 예를 들어 유전 상수가 2.0 에서 2.7 사이의 물질을 사용하는 것이 좋다. 또한 제 2 및 제 3 층간 절연막(3 및 4) 사이에 에치 정지층으로서 하드마스크를 삽입하거나 서로 다른 층간 물질을 사용할 수 있다. 감광막(5 및 50)은 화학 증폭형이며, 크롬(7)이 형성된 레티클(8)을 이용하여 노광한다. 노광시에는 엑시머 레이져를 사용한다. 또한 감광막(50 및 5)은 공정마진과 최적 패턴 뿐만 아니라 감광막의 열적 플로우 공정(resist flow process)을 고려하여 감광막 두께를 결정한다.Referring to FIG. 2C, the second interlayer insulating film 3, the third interlayer insulating film 4, the photosensitive film 50 having the first vitrification temperature, and the second vitrification temperature are disposed on the entire structure including the copper pattern 20. The photosensitive film 5 is formed sequentially. The second and third interlayer insulating films 3 and 4 are formed by chemical vapor deposition, and a material having a low dielectric constant is preferably used, for example, a material having a dielectric constant of 2.0 to 2.7. It is also possible to insert a hard mask as an etch stop layer between the second and third interlayer insulating films 3 and 4 or to use different interlayer materials. The photosensitive films 5 and 50 are chemically amplified and exposed using a reticle 8 having chromium 7 formed thereon. At the time of exposure, an excimer laser is used. In addition, the photoresist layers 50 and 5 determine the photoresist thickness in consideration of the process margin and the optimum pattern as well as the thermal flow process of the photoresist layer.
도 2d 를 참조하면, 현상 공정에 의해 감광막 패턴을 형성한다. 이때, 감광막 패턴의 CD(Critical Dimension)는 원하는 값보다 크게 설정한다(DICD1).Referring to FIG. 2D, a photosensitive film pattern is formed by a developing step. At this time, the CD (Critical Dimension) of the photoresist pattern is set larger than a desired value (DICD1).
도 2e 를 참조하면, 감광막의 열적 플로우 공정전에 노강장비에서 오픈 프레임으로 노광을 실시한다. 이때의 에너지는 DICD1을 형성하기 위해 적용한 노광에너지 보다 훨씬 작은 값으로 해야 한다. 즉, 여러 조건으로 실험하여 최적화된 정도의 에너지를 고려해야 한다. 그 결과로써 감광막의 최외각쪽에만 산(도시안됨)이 발생된다.Referring to Figure 2e, before the thermal flow process of the photosensitive film is exposed to the open frame in the furnace equipment. The energy at this time should be much smaller than the exposure energy applied to form DICD1. In other words, experiments with different conditions should take into account optimized energy levels. As a result, acid (not shown) is generated only at the outermost side of the photosensitive film.
도 2f 를 참조하면, 산이 발생된 감광막(50 및 5)의 유리화 온도를 고려하여 감광막을 플로우 시킨다. 그로인하여 비아홀 형성을 위한 식각 장벽이 되는 감광막 스페이서(5a)가 형성된다. 좀더 구체적으로 설명하면, 유리화 온도가 낮은 감광막(50)이 먼저 플로우되다가 유리화 온도가 높은 감광막(50)이 플로우 되므로 이미 플로우된 감광막이 하부쪽으로 흘러 내려 종래 기술에서 설명한 중간 부분과 아래부분의 차가 없어지게 된다. 즉 오버행이 발생되지 않게 된다. 이때의 감광막 패턴의 폭은 DICD2가 되는데, DICD2 는 DICD1 보다 작게 되는데, 이 자체가 최종적으로 얻고자 하는 홀 크기에 대한 식각 장벽이 될 수 있다.Referring to FIG. 2F, the photoresist film is flowed in consideration of the vitrification temperatures of the photoresist films 50 and 5 in which acid is generated. As a result, the photoresist spacer 5a serving as an etch barrier for forming the via hole is formed. More specifically, since the photosensitive film 50 having a low vitrification temperature is flowed first, and then the photosensitive film 50 having a high vitrification temperature is flowed, the already flowed photosensitive film flows downward and there is no difference between the middle part and the lower part described in the prior art. You lose. That is, no overhang occurs. At this time, the width of the photoresist pattern is DICD2, which is smaller than DICD1, which itself may be an etch barrier for the hole size to be finally obtained.
도 2g 를 참조하면, 감광막 스페이서(5a)가 형성된 감광막 패턴을 마스크로 하여 구리 패턴(20)이 노출될때 까지 제 2 및 제 3 층간 절연막(4)을 제거하는 에칭 공정을 실시한다. 그로인하여 비아홀(100)이 형성된다.Referring to FIG. 2G, an etching process of removing the second and third interlayer insulating films 4 until the copper pattern 20 is exposed using the photosensitive film pattern having the photosensitive film spacer 5a as a mask is performed. As a result, the via hole 100 is formed.
도 2h와 관련하여, 감광막(5 및 50)및 감광막 스페이서(5a)를 제거하고 트랜치 형성을 위한 감감광 패턴(6)을 형성한다. 감광막 패턴(6)형성전에 반사 방지막을 부분적으로 또는 완전히 코팅될 수 있다.2H, the photoresist films 5 and 50 and the photoresist spacers 5a are removed to form a photosensitive pattern 6 for trench formation. The anti-reflection film may be partially or completely coated before the photoresist pattern 6 is formed.
도 2i 를 참조하면, 감광막 패턴(6)을 마스크로 하여 노출된 제 3 층간 절연막(4)를 제거하여 비아홀(100)과 연통되는 트랜치(200)를 형성한다. 이후, 감광막 패턴(6)을 제거하면 듀얼 다마신 패턴이 형성된다. Ta 또는 TaN 등의 구리 확산 방지층과 구리를 증착하고 평탄화 공정을 실시하면 배선 공정이 완료된다.Referring to FIG. 2I, a trench 200 communicating with the via hole 100 is formed by removing the exposed third interlayer insulating layer 4 using the photoresist pattern 6 as a mask. Thereafter, when the photoresist pattern 6 is removed, a dual damascene pattern is formed. The wiring process is completed by depositing a copper diffusion preventing layer such as Ta or TaN and copper and performing a planarization process.
즉, 본 발명에 있어서는 유리화 온도가 서로 다른 감광막의 열적 플로우 공정전에 노광 방비에서 오픈 프레임으로 노광을 실시하고 그 결과로서 감강막의 최외가쪽에서만 산이 발생된다. 산이 발생된 감광막의 유리화 온도를 고려하여 감광막을 플로우 시켜 비아홀 형성을 위한 식각 장벽이 되도록하는 감광막 스페이서가 형성된다. 이때, 유리화 온도가 낮은 감광막이 먼저 플로우되다가 유리화 온도가 높은 감광막이 플로우되면 이미 플로우된 감광막이 하부쪽으로 흘러 내려 감광막 패턴의 중간 부분과 아래부분의 차가 없는 감광막 스페이서가 형성된다. 그로인하여 하부막 식각시 수직한 프로 파일을 얻을 수 있다.That is, in the present invention, exposure is performed in the open frame in the exposure protection before the thermal flow process of the photosensitive film having different vitrification temperatures, and as a result, acid is generated only at the outermost side of the photosensitive film. In consideration of the vitrification temperature of the acid-generated photoresist film, a photoresist spacer is formed to flow the photoresist film to be an etch barrier for forming a via hole. At this time, the photosensitive film having a low vitrification temperature flows first, and when the photosensitive film having a high vitrification temperature flows, the already flown photosensitive film flows downward to form a photosensitive film spacer having no difference between the middle portion and the lower portion of the photosensitive film pattern. As a result, a vertical profile can be obtained when etching the lower layer.
상술한 바와 같이 본 발명에 의하면 어버행이 없는 감광막 패턴을 형성할 수 있으므로 수직한 비아홀 형성이 가능하다. 따라서, 비아홀과 트랜치로 이루어진 듀얼 다마신 구조에 충분히 도전체를 채울 수 있으므로 미세 패턴의 전기적 특성을 향상시킬 수 있다.As described above, according to the present invention, since the photoresist layer pattern without the parent row can be formed, vertical via holes can be formed. Therefore, since the conductor can be sufficiently filled in the dual damascene structure composed of the via hole and the trench, it is possible to improve the electrical characteristics of the fine pattern.
본 발명은 실시예를 중심으로 하여 설명되었으나 당 분야의 통상의 지식을가진 자라면 이러한 실시예를 이용하여 다양한 형태의 변형 및 변경이 가능하므로 본 발명은 이러한 실시예에 한정되는 것이 아니라 다음의 특허 청구 범위에 의해 한정된다.Although the present invention has been described with reference to the embodiments, one of ordinary skill in the art can modify and change various forms using such embodiments, and thus the present invention is not limited to these embodiments. It is limited by the claims.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100715600B1 (en) * | 2005-12-28 | 2007-05-10 | 동부일렉트로닉스 주식회사 | Method of fabricating the fine pattern |
| US9379003B2 (en) | 2012-10-25 | 2016-06-28 | Samsung Electronics Co., Ltd. | Semiconductor structures and methods of manufacturing the same |
| US9613862B2 (en) | 2015-09-02 | 2017-04-04 | International Business Machines Corporation | Chamferless via structures |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100791694B1 (en) * | 2006-11-24 | 2008-01-03 | 동부일렉트로닉스 주식회사 | Method for manufacturing metal line by using dual damascene |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100715600B1 (en) * | 2005-12-28 | 2007-05-10 | 동부일렉트로닉스 주식회사 | Method of fabricating the fine pattern |
| US9379003B2 (en) | 2012-10-25 | 2016-06-28 | Samsung Electronics Co., Ltd. | Semiconductor structures and methods of manufacturing the same |
| US9754817B2 (en) | 2012-10-25 | 2017-09-05 | Samsung Electronics Co., Ltd. | Semiconductor structures having an insulative island structure |
| US9613862B2 (en) | 2015-09-02 | 2017-04-04 | International Business Machines Corporation | Chamferless via structures |
| US10032668B2 (en) | 2015-09-02 | 2018-07-24 | International Business Machines Corporation | Chamferless via structures |
| US10388565B2 (en) | 2015-09-02 | 2019-08-20 | International Business Machines Corporation | Chamferless via structures |
| US10903118B2 (en) | 2015-09-02 | 2021-01-26 | International Business Machines Corporation | Chamferless via structures |
| US10937694B2 (en) | 2015-09-02 | 2021-03-02 | International Business Machines Corporation | Chamferless via structures |
| US10957588B2 (en) | 2015-09-02 | 2021-03-23 | International Business Machines Corporation | Chamferless via structures |
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