KR100257069B1 - Patterning method of semiconductor device - Google Patents

Patterning method of semiconductor device Download PDF

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KR100257069B1
KR100257069B1 KR1019970074380A KR19970074380A KR100257069B1 KR 100257069 B1 KR100257069 B1 KR 100257069B1 KR 1019970074380 A KR1019970074380 A KR 1019970074380A KR 19970074380 A KR19970074380 A KR 19970074380A KR 100257069 B1 KR100257069 B1 KR 100257069B1
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hard mask
layer
conductive layer
patterning
mask layer
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KR19990054551A (en
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하재희
홍승표
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김영환
현대반도체주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas

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  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

PURPOSE: A method for patterning a semiconductor device is to reduce a thickness of a photoresist for patterning a double hard mask layer, thereby easily performing an exposing process. CONSTITUTION: An insulating film(12), the first conductive layer(13), a diffusion stopping layer(14), the second conductive layer(15), and the first and second hard mask layer(16,17) are deposited on a substrate(11). After a photoresist is deposited on the second hard mask layer, the photoresist is patterned so that the photoresist remains on only a conductive pattern region. The second and first hard mask layers are selectively etched using the patterned photoresist as a mask. The second conductive layer, the diffusion stopping film and the first conductive layer are selectively etched using the second and first hard mask layers to form the first conductive layer pattern(15a) and the first conductive layer pattern(13a).

Description

반도체소자의 패터닝 방법Patterning method of semiconductor device

본 발명은 반도체소자의 패터닝방법에 관한 것으로 특히, 패터닝공정후 패턴층의 프로파일의 두께를 적정수준으로 유지하여 신뢰도 높은 반도체소자를 제공할 수 있는 반도체소자의 패터닝방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of patterning a semiconductor device, and more particularly, to a patterning method of a semiconductor device capable of providing a highly reliable semiconductor device by maintaining a thickness of a profile of a pattern layer after a patterning process at an appropriate level.

최근 2, 3년 사이에 고속의 차세대 소자 형성을 위해 저저항 금속 게이트에 대한 관심이 크게 높아지고 있다.In recent two to three years, interest in low-resistance metal gates has increased significantly to form high-speed next-generation devices.

그중에서 비저항이 낮은 텅스텐 게이트에 대한 연구가 최근 많이 발표되고 있다.Among them, many studies on tungsten gate with low resistivity have been recently published.

일반적으로는 게이트의 탄소 오염이나 게이트 산화막에 대한 선택비를 증가시키기 위하여 감광막 대신 산화막이나 질화막과 같은 절연막을 하드 마스크로 사용하고 있다. 그러나, 텅스텐층을 식각할 때 주로 사용되는 불소 플라즈마에서는 하드 마스크와 텅스텐층간의 식각선택비가 1:1이므로 1000Å 정도의 텅스텐 식각시 요구되는 하드 마스크의 두께는 마스크의 패싯(facet)이나 오버에치(overetrch) 등을 고려하여 2000Å 정도가 필요하였다. 또한 후속공정으로 진행되는 LDD공정과 SAC(Self-aligned Contact)공정을 고려하여 최소한 3000Å 정도의 하드 마스크가 요구되었다.In general, an insulating film such as an oxide film or a nitride film is used as a hard mask instead of the photosensitive film in order to increase the carbon contamination of the gate and the selectivity to the gate oxide film. However, in the fluorine plasma mainly used to etch the tungsten layer, the etch selectivity ratio between the hard mask and the tungsten layer is 1: 1, so that the thickness of the hard mask required for the etching of tungsten at about 1000 Å is the facet or over-etch of the mask. Considering overetrch, etc., about 2000mV was needed. In addition, considering the LDD process and the self-aligned contact (SAC) process that follow, a hard mask of at least 3000 의 was required.

이와 같은 종래 반도체소자의 패터닝방법을 첨부된 도면을 참조하여 설명하기로 한다.Such a conventional method of patterning a semiconductor device will be described with reference to the accompanying drawings.

도 1a 내지 도 1c는 종래 반도체소자의 패터닝공정 단면도이다.1A to 1C are cross-sectional views of a patterning process of a conventional semiconductor device.

먼저, 도 1a에 나타낸 바와 같이, 기판(1)상에 산화막(2), 폴리실리콘층(3), 확산방지막(4), 텅스텐층(5) 및 하드 마스크층(6)을 차례로 형성한다. 이어서, 상기 하드 마스크층(6)상에 감광막(PR)을 도포한다. 그다음, 노광 및 현상공정으로 패턴층 영역을 정의하여 패턴층 영역에만 남도록 상기 감광막(PR)을 패터닝한다. 이때, 상기 하드 마스크층(6)은 산화막이나 질화막과 같은 절연막으로 형성하며 상기 폴리실리콘층(3)보다 약 3배 정도의 두께로 형성한다. 즉, 상기 폴리실리콘층(3)은 1000Å의 두께로 형성하였으며, 상기 하드 마스크층(6)은 약 3000Å정도의 두께로 형성한다.First, as shown in FIG. 1A, an oxide film 2, a polysilicon layer 3, a diffusion barrier film 4, a tungsten layer 5, and a hard mask layer 6 are sequentially formed on the substrate 1. Subsequently, a photosensitive film PR is coated on the hard mask layer 6. Subsequently, the photoresist film PR is patterned such that the pattern layer region is defined by an exposure and development process so as to remain only in the pattern layer region. In this case, the hard mask layer 6 is formed of an insulating film such as an oxide film or a nitride film, and is formed to have a thickness about three times that of the polysilicon layer 3. That is, the polysilicon layer 3 is formed to a thickness of 1000 Å, the hard mask layer 6 is formed to a thickness of about 3000 Å.

도 1b에 나타낸 바와 같이, 상기 감광막(PR)을 마스크로 이용한 식각공정으로 상기 하드 마스크층(6)을 선택적으로 제거하여 하드 마스크층 패턴(6a)을 형성한다.As shown in FIG. 1B, the hard mask layer 6 is selectively removed by an etching process using the photoresist film PR as a mask to form a hard mask layer pattern 6a.

도 1c에 나타낸 바와 같이, 상기 하드 마스크층 패턴(6a)을 마스크로 이용한 식각공정으로 상기 텅스텐층(5), 확산방지막(4) 및 폴리실리콘층(3)을 선택적으로 제거하여 폴리실리콘층 패턴(3a)을 형성한다. 이때, 상기한 바와 같은 하드 마스크층 패턴(6a)을 마스크로 이용한 식각공정시 상기 텅스텐층(5) 및 확산방지막(4)은 불소(fluorine) 플라즈마를 이용한 식각공정으로 제거하고, 상기 폴리실리콘층(3)은 염소(chlorine) 플라즈마를 이용한 식각공정으로 제거한다. 그리고, 산화막 또는 질화막으로 형성되는 하드 마스크층 패턴(6a)과 텅스텐층(5)과의 식각 선택비는 1:1이다.As illustrated in FIG. 1C, a polysilicon layer pattern is formed by selectively removing the tungsten layer 5, the diffusion barrier film 4, and the polysilicon layer 3 by an etching process using the hard mask layer pattern 6 a as a mask. (3a) is formed. At this time, in the etching process using the hard mask layer pattern 6a as described above, the tungsten layer 5 and the diffusion barrier 4 are removed by an etching process using a fluorine plasma, and the polysilicon layer is removed. (3) is removed by etching process using chlorine plasma. The etching selectivity between the hard mask layer pattern 6a and the tungsten layer 5 formed of an oxide film or a nitride film is 1: 1.

종래 반도체소자의 패터닝 방법에 있어서는 다음과 같은 문제점이 있었다.The conventional method of patterning semiconductor devices has the following problems.

첫째, 산화막이나 질화막으로 형성되는 하드 마스크층과 텅스텐층과의 식각선택비가 동일하여 하드 마스크층의 두께를 두껍게 형성하므로 전반적으로 종횡비가 증가하며 특히, 하드 마스크층의 하부로 식각공정을 진행할수록 식각공정에 불량이 발생하기 쉬워 폴리실리콘층 패턴의 프로파일 특성이 나빠진다.First, since the etch selectivity between the hard mask layer and the tungsten layer formed of an oxide film or a nitride film is the same, the thickness of the hard mask layer is increased, so the aspect ratio generally increases, and in particular, the etching process is performed to the lower portion of the hard mask layer. It is easy to produce defect in a process, and the profile characteristic of a polysilicon layer pattern worsens.

둘째, 폴리실리콘층 패턴의 프로파일이 불량하여 후속공정으로 LDD영역을 형성하거나 SAC(Self-aligned Contact)공정시 부정확한 공정을 발생시키기 쉬워 신뢰도 높은 반도체소자를 제공하기 어려운 문제점이 있었다.Second, there is a problem that it is difficult to provide a highly reliable semiconductor device because the polysilicon layer pattern has a poor profile, so that an LDD region is formed in a subsequent process or an incorrect process is generated during a self-aligned contact (SAC) process.

본 발명은 상기한 바와 같은 종래 반도체소자의 패터닝 방법의 문제점을 해결하기 위하여 안출한 것으로 전도층의 성능을 향상하기 위하여 전도층의 상측에 고융점금속을 형성한다음 패터닝공정을 실시할 경우에 상기 고융점금속과 전도층을 패터닝하기 위한 마스크층을 각각 구성하여 종횡비를 향상시키고, 후속공정 진행시 신뢰도를 높일수 있는 반도체소자의 패터닝방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the problems of the conventional method of patterning semiconductor devices as described above, when a high melting point metal is formed on the upper side of the conductive layer to improve the performance of the conductive layer. It is an object of the present invention to provide a method for patterning a semiconductor device that can form a mask layer for patterning a high melting point metal and a conductive layer, thereby improving aspect ratio and increasing reliability in a subsequent process.

도 1a 내지 도 1c는 종래 반도체소자의 패터닝공정 단면도1A to 1C are cross-sectional views of a patterning process of a conventional semiconductor device.

도 2a 내지 도 2c는 본 발명 반도체소자의 패터닝공정 단면도2A to 2C are cross-sectional views of a patterning process of a semiconductor device according to the present invention.

도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings

11 : 기판 12 : 절연막11 substrate 12 insulating film

13a : 제 1 전도층 패턴 14 : 확산방지막13a: first conductive layer pattern 14: diffusion barrier film

15a : 제 2 전도층 패턴 16 : 제 1 하드 마스크층15a: second conductive layer pattern 16: first hard mask layer

17 : 제 2 하드 마스크층17: second hard mask layer

본 발명에 따른 반도체소자의 패터닝방법은 기판상에 절연막, 제 1 전도층, 확산방지막, 제 2 전도층 및 제 1, 제 2 하드 마스크층을 차례로 형성하는 단계, 전도층 패턴 영역을 정의하여 전도층 패턴 영역에만 남도록 상기 제 2, 제 1 하드 마스크층을 패터닝하는 단계, 상기 제 2 하드 마스크층을 마스크로 상기 제 2 전도층 및 확산방지막을 선택적으로 제거하고, 상기 제 1 하드 마스크층을 마스크로 상기 제 1 전도층을 선택적으로 제거하는 단계를 포함한다.In the method of patterning a semiconductor device according to the present invention, a step of sequentially forming an insulating film, a first conductive layer, a diffusion barrier, a second conductive layer, and a first and a second hard mask layer on a substrate and defining a conductive layer pattern region is conducted. Patterning the second and first hard mask layers so as to remain only in the layer pattern region, selectively removing the second conductive layer and the diffusion barrier layer using the second hard mask layer as a mask, and masking the first hard mask layer And optionally removing the first conductive layer.

이와 같은 본 발명 반도체소자의 패터닝방법을 첨부된 도면을 참조하여 설명하기로 한다.Such a patterning method of the semiconductor device of the present invention will be described with reference to the accompanying drawings.

도 2a 내지 도 2c는 본 발명 반도체소자의 패터닝공정 단면도이다.2A to 2C are cross-sectional views of a patterning process of a semiconductor device of the present invention.

먼저, 도 2a에 나타낸 바와 같이, 기판(11)상에 절연막(12), 제 1 전도층(13), 확산방지막(14), 제 2 전도층(15)과 제 1 및 제 2 하드 마스크층(16)(17)을 차례로 형성한다. 이어서, 상기 제 2 하드 마스크층(17)상에 감광막(PR)을 도포한다음, 노광 및 현상공정으로 전도층 패턴 영역을 정의하여 전도층 패턴 영역에만 남도록 상기 감광막(PR)을 패터닝한다. 이때, 상기 제 1 전도층(13)은 폴리실리콘층으로 형성하고, 상기 제 2 전도층(15)은 텅스텐과 같은 고융점 금속으로 형성하며, 상기 제 1 하드 마스크층(16)은 산화막이나 질화막과 같은 절연막을 사용하여 형성한다. 그리고, 상기 제 2 하드 마스크층(17)은 상기 제 2 전도층(15)과 1:3이상의 고선택비를 갖는 물질로 형성하며 바람직하게는 Al, Ti, TiN 및 Mo중 어느 하나의 물질로 형성한다. 그리고, 상기 제 2 하드 마스크층(17)은 상기 제 1 하드 마스크층(16)의 1/2 이하의 두께로 형성한다.First, as shown in FIG. 2A, an insulating film 12, a first conductive layer 13, a diffusion barrier 14, a second conductive layer 15, and first and second hard mask layers are formed on a substrate 11. (16) (17) are formed one by one. Subsequently, the photoresist film PR is coated on the second hard mask layer 17, and then the photoresist film PR is patterned so as to remain only in the conductive layer pattern region by defining a conductive layer pattern region in an exposure and development process. In this case, the first conductive layer 13 is formed of a polysilicon layer, the second conductive layer 15 is formed of a high melting point metal such as tungsten, and the first hard mask layer 16 is formed of an oxide film or a nitride film. It is formed using an insulating film such as. In addition, the second hard mask layer 17 may be formed of a material having a high selectivity of 1: 3 or more with the second conductive layer 15. Preferably, the second hard mask layer 17 is formed of any one of Al, Ti, TiN, and Mo. Form. The second hard mask layer 17 is formed to a thickness of 1/2 or less of the first hard mask layer 16.

또한, 상기 제 2 하드 마스크층(17)의 두께는 상기 제 1 전도층(13) 두께의 1/2이하의 두께로 형성한다. 또한, 상기 제 2 하드 마스크층(17)은 염소 플라즈마와 쉽게 반응하는 물질로 형성한다.In addition, the second hard mask layer 17 may have a thickness less than 1/2 of the thickness of the first conductive layer 13. In addition, the second hard mask layer 17 is formed of a material that easily reacts with chlorine plasma.

도 2b에 나타낸 바와 같이, 패터닝된 상기 감광막(PR)을 마스크로 이용한 식각공정으로 상기 제 2, 제 1 하드 마스크층(17)(16)을 선택적으로 제거한다. 그다음, 상기 감광막(PR)을 제거한다.As shown in FIG. 2B, the second and first hard mask layers 17 and 16 are selectively removed by an etching process using the patterned photoresist PR as a mask. Then, the photoresist film PR is removed.

도 2c에 나타낸 바와 같이, 상기 제 2 및 제 1 하드 마스크층(17)(16)을 마스크로 이용한 식각공정으로 상기 제 2 전도층, 확산방지막 및 제 1 전도층(15)(14)(13)을 선택적으로 제거하여 제 2 전도층 패턴(15a) 및 제 1 전도층 패턴(13a)을 형성한다. 이때, 상기한 바와 같은 식각공정은 상기 제 2 하드 마스크층(17)을 이용한 식각공정으로 불소 플라즈마를 이용하여 텅스텐층인 제 2 전도층(15) 및 확산방지막(14)을 식각하고, 이어서, 제 1 하드 마스크층(16)을 마스크로 이용하여 염소 플라즈마를 이용하여 제 1 전도층(13)을 선택적으로 식각하는 것이다. 이때, 상기한 바와 같은 제 2 하드 마스크층(17)은 상기 제 1 전도층(13)과 식각선택비가 유사하여 제 1 전도층(13)을 선택적으로 식각할 때 함께 제거된다. 즉, 제 2 하드 마스크층(17)을 제거하기 위한 별도의 식각공정이 필요없는 것이다.As shown in FIG. 2C, the second conductive layer, the diffusion barrier layer, and the first conductive layer 15, 14, and 13 are formed by an etching process using the second and first hard mask layers 17 and 16 as masks. ) Is selectively removed to form the second conductive layer pattern 15a and the first conductive layer pattern 13a. At this time, the etching process as described above is an etching process using the second hard mask layer 17 to etch the second conductive layer 15 and the diffusion barrier 14, which is a tungsten layer using a fluorine plasma, and then, The first conductive layer 13 is selectively etched using chlorine plasma using the first hard mask layer 16 as a mask. At this time, the second hard mask layer 17 as described above is removed when the first conductive layer 13 is selectively etched because the etching selectivity is similar to that of the first conductive layer 13. That is, a separate etching process for removing the second hard mask layer 17 is not necessary.

본 발명에 따른 반도체소자의 패터닝방법에 있어서는 다음과 같은 효과가 있다.The patterning method of the semiconductor device according to the present invention has the following effects.

첫째, 이중 하드 마스크층을 이용하여 하드 마스크층의 두께를 종래에 비하여 절반가량 줄이므로 이중 하드 마스크층을 패터닝하기 위한 감광막의 두께 또한 줄일 수 있어 초점심도가 향상되므로 노광 및 현상공정이 용이하고, 특히 상측의 하드 마스크는 식각공정 진행중 제거되므로 전반적으로 종횡비가 감소하여 식각 프로파일 및 임계치수(CD : Critical Dimension) 조절이 용이해진다.First, since the thickness of the hard mask layer is reduced by about half by using the double hard mask layer, the thickness of the photosensitive film for patterning the double hard mask layer can also be reduced, and thus the depth of focus is improved, so that the exposure and development processes are easy. In particular, since the upper hard mask is removed during the etching process, the overall aspect ratio is reduced, making it easy to adjust the etching profile and critical dimension (CD).

둘째, 후속공정으로 LDD영역을 형성하거나 SAC 콘택 공정시 정확한 공정진행이 가능하여 신뢰도 높은 반도체소자를 제공할 수 있다.Second, the LDD region may be formed in a subsequent process or an accurate process may be performed during the SAC contact process, thereby providing a highly reliable semiconductor device.

Claims (6)

기판상에 절연막, 제 1 전도층, 확산방지막, 제 2 전도층 및 제 1, 제 2 하드 마스크층을 차례로 형성하는 단계;Sequentially forming an insulating film, a first conductive layer, a diffusion barrier, a second conductive layer, and first and second hard mask layers on the substrate; 전도층 패턴 영역을 정의하여 전도층 패턴 영역에만 남도록 상기 제 2, 제 1 하드 마스크층을 패터닝하는 단계;Defining a conductive layer pattern region and patterning the second and first hard mask layers to remain only in the conductive layer pattern region; 상기 제 2 하드 마스크층을 마스크로 상기 제 2 전도층 및 확산방지막을 선택적으로 제거하고, 상기 제 1 하드 마스크층을 마스크로 상기 제 1 전도층을 선택적으로 제거하는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체소자의 패터닝방법.And selectively removing the second conductive layer and the diffusion barrier layer using the second hard mask layer as a mask, and selectively removing the first conductive layer using the first hard mask layer as a mask. Patterning method of a semiconductor device. 제 1 항에 있어서, 상기 제 2 하드 마스크층은 상기 제 2 전도층과 식각선택비가 1:3 이상인 물질로 형성함을 특징으로 하는 반도체소자의 패터닝방법.The method of claim 1, wherein the second hard mask layer is formed of a material having an etching selectivity of at least 1: 3 with the second conductive layer. 제 2 항에 있어서, 상기 제 2 하드 마스크층은 상기 제 1 전도층을 식각하는 단계에서 제거되는 것을 특징으로 하는 반도체소자의 패터닝방법.The method of claim 2, wherein the second hard mask layer is removed in the etching of the first conductive layer. 제 3 항에 있어서, 상기 제 2 하드 마스크층은 상기 제 1 하드 마스크층의 1/2 이하의 두께로 형성함을 특징으로 하는 반도체소자의 패터닝방법.4. The method of claim 3, wherein the second hard mask layer is formed to a thickness of 1/2 or less of the first hard mask layer. 제 1 항에 있어서, 상기 제 1 전도층은 염소 플라즈마와 반응하여 식각되는 물질로 형성하고, 상기 제 2 전도층은 불소 플라즈마와 반응하여 식각되는 물질임을 특징으로 하는 반도체소자의 패터닝방법.The method of claim 1, wherein the first conductive layer is formed of a material that is etched by reacting with chlorine plasma, and the second conductive layer is a material that is etched by reacting with fluorine plasma. 제 4 항에 있어서, 상기 제 2 하드 마스크층은 알루미늄, 티타늄, 질화티타늄 및 몰리브덴증 어느 하나의 물질로 형성함을 특징으로 하는 반도체소자의 패터닝방법.The method of claim 4, wherein the second hard mask layer is formed of any one of aluminum, titanium, titanium nitride, and molybdenum.
KR1019970074380A 1997-12-26 1997-12-26 Patterning method of semiconductor device KR100257069B1 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6465346B2 (en) 2000-10-31 2002-10-15 Samsung Electronics Co., Ltd. Conducting line of semiconductor device and manufacturing method thereof using aluminum oxide layer as hard mask
KR101062835B1 (en) * 2003-07-14 2011-09-07 주식회사 하이닉스반도체 Method for manufacturing gate electrode of semiconductor device using double hard mask

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6465346B2 (en) 2000-10-31 2002-10-15 Samsung Electronics Co., Ltd. Conducting line of semiconductor device and manufacturing method thereof using aluminum oxide layer as hard mask
KR101062835B1 (en) * 2003-07-14 2011-09-07 주식회사 하이닉스반도체 Method for manufacturing gate electrode of semiconductor device using double hard mask

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