KR100388210B1 - Method for forming metal gate in semiconductor device - Google Patents
Method for forming metal gate in semiconductor device Download PDFInfo
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- KR100388210B1 KR100388210B1 KR10-2001-0037717A KR20010037717A KR100388210B1 KR 100388210 B1 KR100388210 B1 KR 100388210B1 KR 20010037717 A KR20010037717 A KR 20010037717A KR 100388210 B1 KR100388210 B1 KR 100388210B1
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- Prior art keywords
- layer
- metal
- forming
- gate
- nitride film
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 57
- 239000002184 metal Substances 0.000 title claims abstract description 57
- 238000000034 method Methods 0.000 title claims abstract description 21
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 230000004888 barrier function Effects 0.000 claims abstract description 22
- 238000009792 diffusion process Methods 0.000 claims abstract description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 14
- 229920005591 polysilicon Polymers 0.000 claims abstract description 14
- 150000004767 nitrides Chemical class 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000005498 polishing Methods 0.000 claims abstract description 5
- 239000000126 substance Substances 0.000 claims abstract description 5
- 238000005530 etching Methods 0.000 claims abstract description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 6
- 229910052721 tungsten Inorganic materials 0.000 claims description 6
- 239000010937 tungsten Substances 0.000 claims description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 229910008807 WSiN Inorganic materials 0.000 claims description 3
- WNUPENMBHHEARK-UHFFFAOYSA-N silicon tungsten Chemical compound [Si].[W] WNUPENMBHHEARK-UHFFFAOYSA-N 0.000 claims description 3
- -1 tungsten nitride Chemical class 0.000 claims description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims 1
- 238000000059 patterning Methods 0.000 abstract description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021344 molybdenum silicide Inorganic materials 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4941—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
Abstract
본 발명은 반도체 소자의 금속 게이트 형성방법에 관한 것으로, 게이트로 사용되는 금속층 표면을 평탄화하여 게이트 패터닝을 안정적으로 수행할 수 있는 반도체 소자의 금속게이트 형성방법에 관한 것이다.The present invention relates to a method of forming a metal gate of a semiconductor device, and to a method of forming a metal gate of a semiconductor device capable of stably performing gate patterning by planarizing a surface of a metal layer used as a gate.
이를 위한 본 발명의 반도체 소자의 금속 게이트 형성방법은, 기판 상에 제1 절연층, 폴리실리콘층, 확산 방지층, 금속층 및 질화막을 차례로 형성하는 단계; 상기 질화막을 화학기계연마하여 상기 금속층 표면을 평탄화하는 단계; 상기 평탄화된 금속층 상부에 제2 절연층을 형성하는 단계; 상기 제2 절연층을 선택적으로 제거하여 게이트 형상을 한정하는 마스크 패턴을 형성하는 단계; 및 상기 마스크 패턴을 식각 장벽으로 상기 평탄화된 금속층, 확산 방지층, 폴리실리콘층 및 제1 절연층을 차례로 식각하여 금속게이트를 형성하는 단계를 포함하는 반도체 소자의 금속 게이트 형성방법을 제공하는 것을 특징으로 한다.The metal gate forming method of the semiconductor device of the present invention for this purpose, the step of sequentially forming a first insulating layer, a polysilicon layer, a diffusion barrier layer, a metal layer and a nitride film on the substrate; Chemical mechanical polishing the nitride film to planarize the metal layer surface; Forming a second insulating layer on the planarized metal layer; Selectively removing the second insulating layer to form a mask pattern defining a gate shape; And forming a metal gate by sequentially etching the planarized metal layer, the diffusion barrier layer, the polysilicon layer, and the first insulating layer using the mask pattern as an etch barrier, to form a metal gate. do.
Description
본 발명은 반도체소자에 관한 것으로 특히, 반도체소자의 금속게이트 형성방법에 관한 것이다.The present invention relates to a semiconductor device, and more particularly, to a method of forming a metal gate of a semiconductor device.
반도체소자가 고집적화 되면서 고속의 LSI의 필요성이 더욱 커지고 있다.As semiconductor devices are highly integrated, the need for high-speed LSI is increasing.
이를 만족시키기 위해서 저항이 낮은 금속게이트에 대한 관심이 커지고 있는 추세이다. 이중 폴리실리콘층 상에 텅스텐층(W) 또는 몰리브덴층(Mo) 또는 실리사이드층이 형성된 금속게이트의 전기적특성에 대한 연구가 계속되고 있다.In order to satisfy this, interest in metal gates with low resistance is increasing. Research on the electrical characteristics of the metal gate formed with the tungsten layer (W), molybdenum layer (Mo) or silicide layer on the double polysilicon layer is continuing.
이하, 종래기술에 따른 금속게이트 형성방법을 첨부된 도면을 참조하여 설명하기로 한다.Hereinafter, a method of forming a metal gate according to the prior art will be described with reference to the accompanying drawings.
도 1a 내지 1c는 종래 금속게이트 형성방법을 설명하기 위한 공정단면도이다.1A to 1C are cross-sectional views illustrating a conventional method for forming a metal gate.
먼저, 도 1a에 도시한 바와같이, 실리콘 기판(11)상에 제 1 절연층(12)을 형성하고, 상기 제 1 절연층(12)상에 폴리실리콘층(13)을 형성한다. 이어서, 폴리실리콘층(13)상에 확산방지층(14)을 형성하고, 확산방지층(14) 상에 금속층(15)을 형성한다. 여기서, 상기 확산방지층(14)은 티타늄나이트라이드(TiN) 또는 텅스텐실리콘나이트라이드(WSiN)를 사용한다. 그리고, 상기 금속층(15)으로써는 텅스텐, 몰리브덴, 텅스텐 실리사이드, 몰리브텐 실리사이드층 중 어느 하나를 사용한다.First, as shown in FIG. 1A, a first insulating layer 12 is formed on a silicon substrate 11, and a polysilicon layer 13 is formed on the first insulating layer 12. Subsequently, the diffusion barrier layer 14 is formed on the polysilicon layer 13, and the metal layer 15 is formed on the diffusion barrier layer 14. Here, the diffusion barrier layer 14 uses titanium nitride (TiN) or tungsten silicon nitride (WSiN). As the metal layer 15, any one of tungsten, molybdenum, tungsten silicide, and molybdenum silicide layer is used.
그 다음, 상기 금속층(15)상에 하드 마스크용 제 2 절연층(16)을 형성하며, 상기 제 2 절연층(16)상에 포토레지스트를 도포한다. 그 다음 노광 및 현상공정으로 게이트 형상을 한정하는 포토레지스트 패턴(17)을 형성한다.Next, a second insulating layer 16 for hard mask is formed on the metal layer 15, and a photoresist is applied on the second insulating layer 16. The photoresist pattern 17 is then formed to define the gate shape by exposure and development.
이어서, 도 1b에 도시한 바와같이, 상기 포토레지스트 패턴(17)을 식각 장벽으로 상기 제 2 절연층(16)을 선택적으로 제거하여 마스크 패턴(16a)을 형성한다.Subsequently, as shown in FIG. 1B, the second insulating layer 16 is selectively removed using the photoresist pattern 17 as an etch barrier to form a mask pattern 16a.
그 다음, 도 1c에 도시한 바와같이, 포토레지스트 패턴(17)을 제거하고, 상기 마스크 패턴(16a)을 식각 장벽으로 금속층(15), 확산방지층(14), 그리고 폴리실리콘층(13)을 차례로 패터닝하여 금속게이트를 형성한다.Next, as shown in FIG. 1C, the photoresist pattern 17 is removed, and the metal layer 15, the diffusion barrier layer 14, and the polysilicon layer 13 are formed using the mask pattern 16a as an etch barrier. Patterned in turn to form a metal gate.
이후, 계속해서 트랜지스터 공정 예컨대, 게이트 양측벽에 LDD(Lightly Doped Drain) 영역을 형성하기 위한 스페이서 및 게이트 양측의 실리콘 기판내에 형성된 소오스/드레인 영역의 형성 공정 등을 수행하여 반도체 소자를 제조한다.Subsequently, a semiconductor device is manufactured by performing a transistor process, for example, a spacer for forming an LDD (Lightly Doped Drain) region on both sidewalls of the gate and a source / drain region formed in the silicon substrate on both sides of the gate.
그러나, 상기 금속게이트로 사용되는 금속층은 그 표면의 거칠기 문제로 상기 게이트 패터닝시 디파인(define) 문제, 신뢰성 문제를 야기시켜 커런트의 불안정성을 유발한다.However, the metal layer used as the metal gate causes a fineness problem and a reliability problem during patterning of the gate due to the roughness of the surface, resulting in instability of the current.
따라서, 상기 문제점을 해결하기 위해 안출된 본 발명의 목적은 게이트로 사용되는 금속층 표면을 평탄화하여 게이트 패터닝을 안정적으로 수행할 수 있는 반도체 소자의 금속게이트 형성방법을 제공하는 데 있다.Accordingly, an object of the present invention devised to solve the above problems is to provide a method of forming a metal gate of a semiconductor device capable of stably performing gate patterning by planarizing a surface of a metal layer used as a gate.
도 1a 내지 도 1c는 종래의 반도체 소자의 금속 게이트 형성방법을 설명하기 위한 제조공정도.1A to 1C are manufacturing process diagrams for explaining a metal gate forming method of a conventional semiconductor device.
도 2a 내지 도 2e는 본 발명의 반도체 소자의 금속 게이트 형성방법을 설명하기 위한 제조공정도.2A to 2E are manufacturing process diagrams for explaining a metal gate forming method of a semiconductor device of the present invention.
* 도면의 주요부분에 대한 부호 설명 *Explanation of symbols on the main parts of the drawings
30 : 실리콘 기판 32 : 제1 절연층30 silicon substrate 32 first insulating layer
34 : 폴리실리콘층 36 : 확산 방지층34 polysilicon layer 36 diffusion barrier layer
38 : 금속층 38a : 평탄화된 금속층38 metal layer 38a flattened metal layer
40 : 질화막 42 : 제2 절연층40: nitride film 42: second insulating layer
42a : 마스크 패턴 44 : 포토 레지스트 패턴42a: mask pattern 44: photoresist pattern
상기 목적 달성을 위한 본 발명의 반도체 소자의 금속 게이트 형성방법은, 기판 상에 제1 절연층, 폴리실리콘층, 확산 방지층, 금속층 및 질화막을 차례로 형성하는 단계; 상기 질화막을 화학기계연마하여 상기 금속층 표면을 평탄화하는 단계; 상기 평탄화된 금속층 상부에 제2 절연층을 형성하는 단계; 상기 제2 절연층을 선택적으로 제거하여 게이트 형상을 한정하는 마스크 패턴을 형성하는 단계; 및 상기 마스크 패턴을 식각 장벽으로 상기 평탄화된 금속층, 확산 방지층, 폴리실리콘층 및 제1 절연층을 차례로 식각하여 금속게이트를 형성하는 단계를 포함하는 반도체 소자의 금속 게이트 형성방법을 제공하는 것을 특징으로 한다.Metal gate forming method of a semiconductor device of the present invention for achieving the above object, the step of sequentially forming a first insulating layer, a polysilicon layer, a diffusion barrier layer, a metal layer and a nitride film on the substrate; Chemical mechanical polishing the nitride film to planarize the metal layer surface; Forming a second insulating layer on the planarized metal layer; Selectively removing the second insulating layer to form a mask pattern defining a gate shape; And forming a metal gate by sequentially etching the planarized metal layer, the diffusion barrier layer, the polysilicon layer, and the first insulating layer using the mask pattern as an etch barrier, to form a metal gate. do.
이하, 본 발명의 바람직한 실시예를 첨부한 도면을 참조하여 상세히 설명한다.Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in detail.
도 2a 내지 도 2e는 본 발명의 반도체 소자의 금속 게이트 형성방법을 설명하기 위한 각 단계별 공정 단면도이다.2A to 2E are cross-sectional views of steps for explaining a method of forming a metal gate of a semiconductor device according to the present invention.
먼저, 도 2a에 도시된 바와같이, 소자 분리막(미도시)이 형성된 실리콘 기판(30)을 제공한다. 상기 실리콘 기판(30) 상부에 제1 절연층(32), 폴리실리콘층(34), 확산 방지층(36), 금속층(38) 및 질화막(40)을 차례로 적층하여 증착한다.First, as shown in FIG. 2A, a silicon substrate 30 having an isolation layer (not shown) is provided. The first insulating layer 32, the polysilicon layer 34, the diffusion barrier layer 36, the metal layer 38, and the nitride film 40 are sequentially deposited on the silicon substrate 30.
이때, 확산 방지층(36)은 상기 폴리실리콘층(34)과 금속층(38)과의 상호 반응을 제어하기 위한 목적으로, 바람직하게 티타늄 질화막(TiN), 텅스텐실리콘질화막(WSiN) 중 어느 하나를 선택하여 형성한다.In this case, the diffusion barrier layer 36 is preferably selected from one of a titanium nitride film (TiN) and a tungsten silicon nitride film (WSiN) for the purpose of controlling the mutual reaction between the polysilicon layer 34 and the metal layer 38. To form.
그리고, 상기 금속층(38)은 텅스텐, 텅스텐 질화막, 티타늄 질화막중 어느 하나를 선택하여 형성하며, 바람직하게는 1000Å ~ 2000Å 두께로 PVD(Plasma Vapor Deposition) 또는 CVD(Chemical Vapor Deposition) 방식에 의해 형성된다.The metal layer 38 is formed by selecting any one of tungsten, a tungsten nitride film, and a titanium nitride film. Preferably, the metal layer 38 is formed by a plasma vapor deposition (PVD) or chemical vapor deposition (CVD) method with a thickness of 1000 kPa to 2000 kPa. .
그리고, 상기 질화막(40)은 100Å ~ 1000Å 두께로 증착됨이 바람직하다.In addition, the nitride film 40 is preferably deposited to a thickness of 100 ~ 1000 Å.
그 다음, 도 2b에 도시된 바와같이, 질화막(40)을 화학기계연마하여 상기 금속층 표면을 평탄화한다. 이때, 상기 화학기계연마를 통하여 금속층(38)의 두께는 바람직하게 300 ∼1000Å이 된다. 이러한 평탄화로 인해 종래의 문제점으로 작용하는 금속층의 거칠기 문제를 해결할 수 있다.Next, as shown in FIG. 2B, the nitride film 40 is chemically mechanically polished to planarize the metal layer surface. At this time, the thickness of the metal layer 38 is preferably 300 to 1000 kPa through the chemical mechanical polishing. Such planarization may solve the roughness problem of the metal layer, which serves as a conventional problem.
이어서, 도 2c에 도시된 바와같이, 평탄화된 금속층(38a) 상부에 제2 절연층(42)을 증착한다. 제2 절연층(42)은 바람직하게 하드마스크용 질화막으로 증착된다. 그런다음, 제2 절연층(42) 상부에 포토레지스트를 도포한다. 그리고나서, 노광 및 현상공정으로 게이트 형상을 한정하는 포토레지스트 패턴(44)을 형성한다.Next, as shown in FIG. 2C, a second insulating layer 42 is deposited on the planarized metal layer 38a. The second insulating layer 42 is preferably deposited with a nitride film for hard mask. Then, photoresist is applied on the second insulating layer 42. Then, the photoresist pattern 44 defining the gate shape is formed by the exposure and development processes.
그 다음, 도 2d에 도시된 바와같이, 상기 포토레지스트 패턴을 식각 장벽으로 상기 제 2 절연층을 선택적으로 제거하여 마스크 패턴(42a)을 형성한다.Next, as shown in FIG. 2D, the second insulating layer is selectively removed using the photoresist pattern as an etch barrier to form a mask pattern 42a.
이어서, 도 2e에 도시된 바와같이, 포토레지스트 패턴(44)을 제거하고, 상기 마스크 패턴(42a)을 식각 장벽으로 평탄화된 금속층(38a), 확산방지층(36), 폴리실리콘층(34) 및 제1 절연층(32)을 차례로 패터닝하여 금속게이트를 형성한다.Subsequently, as shown in FIG. 2E, the photoresist pattern 44 is removed, and the metal layer 38a, the diffusion barrier layer 36, the polysilicon layer 34, and the mask pattern 42a are planarized with an etch barrier. The first insulating layer 32 is sequentially patterned to form a metal gate.
이후, 계속해서 트랜지스터 공정 예컨대, 게이트 양측벽에 LDD(Lightly Doped Drain) 영역을 형성하기 위한 스페이서 및 게이트 양측의 실리콘 기판내에 형성된 소오스/드레인 영역의 형성 공정 등을 수행하여 반도체 소자를 제조한다.Subsequently, a semiconductor device is manufactured by performing a transistor process, for example, a spacer for forming an LDD (Lightly Doped Drain) region on both sidewalls of the gate and a source / drain region formed in the silicon substrate on both sides of the gate.
한편, 이상에서 설명한 본 발명은 상술한 실시예 및 첨부된 도면에 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위내에서 여러가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.On the other hand, the present invention described above is not limited to the above-described embodiment and the accompanying drawings, it is possible in the technical field of the present invention that various substitutions, modifications and changes are possible without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.
상술한 본 발명의 반도체 소자의 금속 게이트 형성방법에 의하면, 금속 게이트의 표면 거칠기를 화학기계연마를 통하여 제어함으로써, 게이트 패터닝시 디파인(define) 문제를 제어할 수 있으며, 미세 선폭의 패터닝을 용이하게 할 수있다.According to the method for forming a metal gate of the semiconductor device of the present invention described above, by controlling the surface roughness of the metal gate through chemical mechanical polishing, it is possible to control the problem of fineness during gate patterning, and to easily pattern the fine line width. can do.
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