KR100406581B1 - method of manufacturing semiconductor device - Google Patents
method of manufacturing semiconductor device Download PDFInfo
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- KR100406581B1 KR100406581B1 KR10-2001-0079825A KR20010079825A KR100406581B1 KR 100406581 B1 KR100406581 B1 KR 100406581B1 KR 20010079825 A KR20010079825 A KR 20010079825A KR 100406581 B1 KR100406581 B1 KR 100406581B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 60
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 29
- 239000010949 copper Substances 0.000 claims abstract description 19
- 239000011229 interlayer Substances 0.000 claims abstract description 18
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 17
- 229910052802 copper Inorganic materials 0.000 claims abstract description 17
- 239000010410 layer Substances 0.000 claims abstract description 16
- 125000006850 spacer group Chemical group 0.000 claims abstract description 16
- 230000009977 dual effect Effects 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims abstract description 9
- 238000005498 polishing Methods 0.000 claims abstract description 9
- 238000000151 deposition Methods 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 239000000126 substance Substances 0.000 claims abstract description 6
- 238000001312 dry etching Methods 0.000 claims abstract description 4
- 230000001678 irradiating effect Effects 0.000 claims abstract description 4
- 238000007747 plating Methods 0.000 claims abstract description 3
- 239000000463 material Substances 0.000 claims description 7
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 238000007740 vapor deposition Methods 0.000 abstract 1
- 229910052751 metal Inorganic materials 0.000 description 22
- 239000002184 metal Substances 0.000 description 22
- 238000001459 lithography Methods 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000007792 addition Methods 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 노광장비를 한번만 사용하고 감광막의 열적 흐름 공정을 이용하여 감광막 스페이서 패턴을 완성하고 이를 이용한 듀얼 다마신 패턴을 형성함으로써, 구리 배선 형성 공정을 단순화시킬 수 있고 디바이스의 제조시 원가를 절감할 수 있다. 이를 위한 본 발명의 반도체 소자의 제조 방법은 반도체 기판 위에 제 1 층간절연막을 형성하는 단계와, 상기 제 1 층간절연막의 소정 부분을 감광막 패턴에 의해 식각하여 구리배선이 형성될 패턴을 형성하는 단계와, 상기 구조물 위에 구리를 도금 방법으로 증착한 후 화학적기계연마(CMP) 공정으로 상기 제 1 절연막이 드러날 때까지 연마하여 표면을 평탄화하는 단계와, 상기 구조물 위에 제 2 절연막, 제 3 절연막을 플라즈마 화학 기상 증착법으로 차례로 증착하는 단계와, 상기 제 3 절연막 위에 포지티브 화학증폭형 감광막을 형성한 다음, 레티클을 통해 엑시머 레이저를 조사하여 상기 포지티브 화학증폭형 감광막 패턴을 형성하는 단계와, 상기 포지티브 화학증폭형 감광막 패턴을 이용하여 상기 제 3 절연막을 식각하여 트렌치 패턴을 형성한 단계와, 상기 포지티브 화학증폭형 감광막의 열적 플로우를 이용하여 상기 트렌치 패턴의 내부 측면에 감광막 스페이서를 형성하는 단계와, 상기 감광막 스페이서를 이용하여 상기 제 2 절연막을 건식 식각하는 단계와, 상기 감광막 스페이서를 제거하여 듀얼다마신 패턴을 형성하는 단계를 포함하는 것을 특징으로 한다.The present invention relates to a method for manufacturing a semiconductor device, and by using the exposure equipment only once and completing the photoresist spacer pattern by using the thermal flow process of the photoresist and forming a dual damascene pattern using the same, thereby simplifying the copper wiring formation process. And cost reduction in the manufacture of the device. A method of manufacturing a semiconductor device according to the present invention may include forming a first interlayer insulating film on a semiconductor substrate, etching a predetermined portion of the first interlayer insulating film by a photosensitive film pattern, and forming a pattern on which a copper wiring is to be formed; Depositing copper on the structure by a plating method and then polishing it until the first insulating film is exposed by a chemical mechanical polishing (CMP) process to planarize the surface; and depositing the second insulating film and the third insulating film on the structure by plasma chemical Depositing sequentially by vapor deposition, forming a positive chemically amplified photosensitive film on the third insulating film, and then irradiating an excimer laser through a reticle to form the positive chemically amplified photosensitive film pattern, and the positive chemically amplified type Forming a trench pattern by etching the third insulating layer using a photoresist pattern Forming a photoresist spacer on an inner side surface of the trench pattern by using a thermal flow of the positive chemically amplified photoresist, dry etching the second insulating layer using the photoresist spacer, and removing the photoresist spacer To form a dual damascene pattern characterized in that it comprises a.
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 포토리소그래피공정에서 감광막 패턴의 열적 플로우를 이용한 미세패턴형성에 관한 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device for forming a fine pattern using a thermal flow of a photosensitive film pattern in a photolithography process.
일반적으로, 금속배선은 두 가지 방법으로 형성되고 있다.In general, metal wiring is formed in two ways.
첫번째 방법은 금속막 상에 감광막 패턴을 형성하고, 그런다음, 상기 감광막 패턴을 식각 장벽으로 하는 플라즈마 식각 공정으로 상기 금속막을 직접 식각하여 소망하는 형태의 금속배선을 형성하는 방법이다. 그런데, 이 방법은 금속배선의 임계 치수(critical dimension)가 감소되고 있는 추세에서, 그 전기적 특성의 확보가 매우 어려운 문제점이 있다.The first method is a method of forming a photoresist pattern on a metal film, and then directly etching the metal film by a plasma etching process using the photoresist pattern as an etching barrier to form a metal wiring in a desired form. However, this method has a problem that it is very difficult to secure the electrical characteristics in the trend that the critical dimension of the metal wiring is reduced.
두번째 방법은 다마신(damascene) 공정을 이용한 방법으로서, 먼저, 제1층간절연막의 일부분을 식각·제거하여 콘택홀을 형성한 후, 상기 콘택홀 내에 금속막을 매립시켜 금속 플러그를 형성하고, 그런다음, 상기 결과물 상에 제2층간절연막을 형성한 후, 상기 제2층간절연막을 식각하여 상기 금속 플러그를 노출시킴과 동시에 라인 형태를 갖는 스페이싱 패턴(spacing pattern)을 형성하고, 그리고나서, 상기 스페이싱 패턴 내에 금속막을 매립시켜, 상기 금속 플러그와 콘택되는 금속배선을 형성하는 방법이다. 이 방법은 전자의 방법 보다 상대적으로 우수한 전기적 특성을 얻을 수 있으며, 아울러, 공정 비용이 적기 때문에, 점차 그 이용이 확대되고 있다.The second method is a method using a damascene process. First, a portion of the first interlayer insulating layer is etched and removed to form a contact hole, and then a metal film is embedded in the contact hole to form a metal plug. After forming a second interlayer insulating film on the resultant, the second interlayer insulating film is etched to expose the metal plug, and a spacing pattern having a line shape is formed. Then, the spacing pattern is formed. A metal film is embedded in the metal film to form a metal wiring in contact with the metal plug. This method is able to obtain relatively superior electrical characteristics than the former method, and at the same time, the use of the method is gradually expanded because of less process cost.
도 1a 내지 도 1c는 종래 기술에 따른 다마신 공정을 이용한 반도체 소자의 금속배선 형성방법을 설명하기 위한 공정 단면도이다.1A to 1C are cross-sectional views illustrating a method of forming metal wirings of a semiconductor device using a damascene process according to the prior art.
도 1a를 참조하면, 트랜지스터 등과 같은 하부 패턴들(도시안됨)이 형성된 반도체 기판(1) 상에 상기 하부 패턴들을 덮도록 제1층간절연막(2) 및 제1하드 마스크막(3)을 차례로 형성하고, 공지된 방법으로 상기 제1하드 마스크막(30) 및 제1층간절연막(2)을 식각해서, 반도체 기판(1)의 일부분 또는 하부 패턴을 노출시키는 콘택홀(4)을 형성한다.Referring to FIG. 1A, a first interlayer insulating film 2 and a first hard mask film 3 are sequentially formed on a semiconductor substrate 1 on which lower patterns (not shown), such as a transistor, are formed to cover the lower patterns. The first hard mask film 30 and the first interlayer insulating film 2 are etched by a known method to form a contact hole 4 exposing a portion or a lower pattern of the semiconductor substrate 1.
도 1b를 참조하면, 콘택홀(4)이 완전히 매립될 정도의 충분한 두께로 상기 제1하드 마스크막(3) 상에 금속막을 증착하고, 상기 제1하드 마스크막(3)이 노출되도록, 상기 금속막을 화학적기계연마(Chemacal Mechanical Polishing: CMP) 공정으로 연마하여 표면 평탄화를 얻음과 동시에 상기 콘택홀(4) 내에 금속 플러그(5)을 형성한다.Referring to FIG. 1B, a metal film is deposited on the first hard mask film 3 to a sufficient thickness such that the contact hole 4 is completely filled, and the first hard mask film 3 is exposed. The metal film is polished by a chemical mechanical polishing (CMP) process to obtain surface planarization and to form a metal plug 5 in the contact hole 4.
도 1c를 참조하면, 상기 결과물의 상부에 저유전상수 값을 갖는 제2층간절연막(6)과 제2하드 마스크막(7)을 차례로 형성하고, 공지된 방법으로 상기 제2하드 마스크막(7) 및 제2층간절연막(6)을 플라즈마 식각해서, 상기 금속 플러그(5) 및 이에 인접된 제1하드 마스크막 부분을 노출시키는 라인 형태의 스페이싱 패턴(8)을 형성한다. 그런다음, 상기 스페이싱 패턴(8) 내에 금속막을 매립시켜, 상기 금속 플러그(5)와 콘택되는 금속배선(9)를 형성한다.Referring to FIG. 1C, a second interlayer insulating film 6 having a low dielectric constant value and a second hard mask film 7 are sequentially formed on the resultant, and the second hard mask film 7 is well known. And plasma etching the second interlayer insulating film 6 to form a line-type spacing pattern 8 exposing the metal plug 5 and a portion of the first hard mask film adjacent thereto. Then, a metal film is embedded in the spacing pattern 8 to form a metal wiring 9 in contact with the metal plug 5.
일반적으로, 배선 재료로 사용되고 있는 알루미늄은 비저항이 2.7μΩ㎝로서 현존하는 금속중에서 4번째로 낮은 비저항을 갖고 있으며 우수한 전기전도도를 나타내고 있어 디바이스의 제작시 적용되고 있다. 그러나, 알루미늄은 질량 이동(Mass Transport)에 기인한 빈공간(Void)과 언덕(Hillock)을 형성하는 일렉트로마이그레이션(Electromigration: EM)에 대한 저항성이 열악한 것으로 알려져 있다.In general, aluminum, which is used as a wiring material, has a specific resistivity of 2.7 µΩcm, has the fourth lowest resistivity among existing metals, and shows excellent electrical conductivity, which is applied in the manufacture of devices. However, aluminum is known to have poor resistance to electromigration (EM), which forms voids and hills due to mass transport.
이에 대한 차세대 배선재료로 비저항이 1.7μΩ㎝이며 알루미늄에 비해 일렉트로마이그레이션(EM)에 대한 저항성이 우수한 구리가 대안으로 자리잡고 있다.The next generation wiring material is copper, which has a specific resistance of 1.7 µΩcm and is more resistant to electromigration (EM) than aluminum.
구리를 배선재료로 사용하기 위해서는 일반적으로 비아 콘택홀 및 배선영역을 정의하는 듀얼 다마신(Dual Damascene) 패턴 형성 방법이 사용되고 있다.In order to use copper as a wiring material, a dual damascene pattern forming method for defining a via contact hole and a wiring area is generally used.
듀얼 다마신 공정 순서는 비아 리소그래피, 비아 식각과 스트립, 트랜치 리소그래피, 트랜치 식각과 스트립 또는 트랜치 리소그래피, 트랜치 식각과 스트립, 비아 리소그래피, 비아 식각과 스트립의 순으로 이루어진다.The dual damascene process sequence consists of via lithography, via etch and strip, trench lithography, trench etch and strip or trench lithography, trench etch and strip, via lithography, via etch and strip.
그러나, 듀얼 다마신 공정을 이용하는 종래의 반도체 소자의 제조 방법에 있어서는 스텝퍼나 스캐너 등의 노광장비에서의 노광공정이 두번 사용됨으로써 양산 스루프(throughput)가 감소되며, 이로 인해 디바이스 제조에 따른 원가의 상승을 초래하게 되는 문제점이 있었다.However, in the conventional method of manufacturing a semiconductor device using the dual damascene process, the exposure process in exposure equipment such as a stepper or a scanner is used twice, thereby reducing the production throughput. There was a problem that caused the rise.
따라서, 본 발명은 상기 문제점을 해결하기 위하여 이루어진 것으로, 본 발명은 노광장비를 한번만 사용하고 감광막의 열적 흐름 공정(Resist Flow Process)을 이용하여 감광막 스페이서 패턴을 완성하고 이를 이용한 듀얼 다마신 패턴을 형성함으로써, 구리 배선 형성 공정을 단순화시킬 수 있고 디바이스의 제조시 원가를 절감할 수 있는 반도체 소자의 제조 방법을 제공하는데 그 목적이 있다.Accordingly, the present invention has been made to solve the above problems, the present invention is to use the exposure equipment only once and to complete the photoresist spacer pattern using the resist flow process (Resist Flow Process) and to form a dual damascene pattern using the same Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device, which can simplify a copper wiring forming process and can reduce costs in manufacturing a device.
도 1a 내지 도 1c는 종래 기술에 따른 다마신 공정을 이용한 반도체 소자의 금속배선 형성방법을 설명하기 위한 공정 단면도1A to 1C are cross-sectional views illustrating a method of forming metal wirings of a semiconductor device using a damascene process according to the related art.
도 2a 내지 도 2h는 본 발명에 의한 반도체 소자의 제조 방법을 설명하기 위한 제조공정 단면도2A to 2H are cross-sectional views of the manufacturing process for explaining the method for manufacturing a semiconductor device according to the present invention.
(도면의 주요 부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)
1 : 제 1 절연막 2 : 구리1: first insulating film 2: copper
3 : 제 2 절연막 4 : 제 3 절연막3: second insulating film 4: third insulating film
5 : 감광막 6 : 감광막 스페이서5: photosensitive film 6: photosensitive film spacer
7 : 크롬 8 : 레티클7: chrome 8: reticle
10 : 반도체 기판10: semiconductor substrate
상기 목적을 달성하기 위한 본 발명의 반도체 소자의 제조 방법은,The semiconductor device manufacturing method of the present invention for achieving the above object,
반도체 기판 위에 제 1 층간절연막을 형성하는 단계와,Forming a first interlayer insulating film on the semiconductor substrate,
상기 제 1 층간절연막의 소정 부분을 감광막 패턴에 의해 식각하여 구리배선이 형성될 패턴을 형성하는 단계와,Forming a pattern on which a copper wiring is to be formed by etching a predetermined portion of the first interlayer insulating film by a photosensitive film pattern;
상기 구조물 위에 구리를 도금 방법으로 증착한 후 화학적기계연마(CMP) 공정으로 상기 제 1 절연막이 드러날 때까지 연마하여 표면을 평탄화하는 단계와,Depositing copper on the structure by a plating method, and then polishing the surface of the first insulating layer by a chemical mechanical polishing (CMP) process to planarize the surface;
상기 구조물 위에 제 2 절연막, 제 3 절연막을 플라즈마 화학 기상 증착법으로 차례로 증착하는 단계와,Sequentially depositing a second insulating film and a third insulating film on the structure by plasma chemical vapor deposition;
상기 제 3 절연막 위에 포지티브 화학증폭형 감광막을 형성한 다음, 레티클을 통해 엑시머 레이저를 조사하여 상기 포지티브 화학증폭형 감광막 패턴을 형성하는 단계와,Forming a positive chemically amplified photosensitive film on the third insulating film, and then irradiating an excimer laser through a reticle to form the positive chemically amplified photosensitive film pattern;
상기 포지티브 화학증폭형 감광막 패턴을 이용하여 상기 제 3 절연막을 식각하여 트렌치 패턴을 형성한 단계와,Etching the third insulating layer using the positive chemically amplified photosensitive film pattern to form a trench pattern;
상기 포지티브 화학증폭형 감광막의 열적 플로우를 이용하여 상기 트렌치 패턴의 내부 측면에 감광막 스페이서를 형성하는 단계와,Forming a photoresist spacer on an inner side surface of the trench pattern using a thermal flow of the positive chemically amplified photoresist;
상기 감광막 스페이서를 이용하여 상기 제 2 절연막을 건식 식각하는 단계와,Dry etching the second insulating layer using the photoresist spacer;
상기 감광막 스페이서를 제거하여 듀얼다마신 패턴을 형성하는 단계를 포함하는 것을 특징으로 한다.Removing the photoresist spacer to form a dual damascene pattern.
상기 제 2 및 제 3 절연막은 유전상수(k)가 작은 물질(k=2.0∼2.7)을 사용하는 것을 특징으로 한다.The second and third insulating films may be formed of a material having a small dielectric constant k (k = 2.0 to 2.7).
상기 제 2 및 제 3 절연막 사이에 식각 정지층으로 하드마스크를 사용하는 것을 특징으로 한다.A hard mask may be used as an etch stop layer between the second and third insulating layers.
이하, 본 발명의 실시예에 관하여 첨부도면을 참조하면서 상세히 설명한다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
또, 실시예를 설명하기 위한 모든 도면에서 동일한 기능을 갖는 것은 동일한 부호를 사용하고 그 반복적인 설명은 생략한다.In addition, in all the drawings for demonstrating an embodiment, the thing with the same function uses the same code | symbol, and the repeated description is abbreviate | omitted.
도 2a 내지 도 2h는 본 발명에 의한 반도체 소자의 제조 방법을 설명하기 위한 제조공정 단면도이다.2A to 2H are cross-sectional views of the manufacturing process for explaining the method for manufacturing a semiconductor device according to the present invention.
먼저, 도 2a에 도시된 공정은, 반도체 기판(10) 위에 저유전물질인 제 1 층간절연막(1)을 플라즈마 화학 기상 증착(Plasma Enhanced Chemical Vaporization Deposition)법으로 증착한다.First, the process illustrated in FIG. 2A deposits a first dielectric interlayer film 1 of low dielectric material on the semiconductor substrate 10 by plasma enhanced chemical vapor deposition deposition.
다음, 상기 제 1 층간절연막(1) 위에 감광막을 도포하여 구리배선을 형성하기 위한 마스크 패턴(도시하지 않음)을 형성한 후 노광을 하여 상기 제 1 층간절연막(1)의 소정 부분을 식각한다.Next, a photosensitive film is applied on the first interlayer insulating film 1 to form a mask pattern (not shown) for forming copper wiring, and then exposed to light to etch a predetermined portion of the first interlayer insulating film 1.
다음, 상기 구조물 위에 구리(Cu)(2)를 도금(Electroplating) 방법으로 증착한 단계이다.Next, copper (Cu) 2 is deposited on the structure by an electroplating method.
도 2b에 도시된 공정은, 상기 구리(Cu)(2)를 화학적기계연마(Chemacal Mechanical Polishing: CMP) 공정으로 상기 제 1 절연막(1)이 드러날 때까지 연마하여 표면을 평탄화시킨 단계이다.The process shown in FIG. 2B is a step of polishing the copper (Cu) 2 by a chemical mechanical polishing (CMP) process until the first insulating film 1 is exposed to planarize the surface.
도 2c에 도시된 공정은, 도 2b의 구조물 위에 제 2 절연막(3), 제 3 절연막(4)을 플라즈마 화학 기상 증착법으로 차례로 증착한다.In the process shown in FIG. 2C, the second insulating film 3 and the third insulating film 4 are sequentially deposited on the structure of FIG. 2B by plasma chemical vapor deposition.
이때, 제 2 및 제 3 절연막(3)(4)은 유전상수가 작은 물질{low-k; k값의 범위는 2.0에서 2.7 사이}을 선택한다. 그리고, 제 2 및 제 3 절연막(3)(4) 사이에식각 정지층(Etch Stop Layer)으로 하드마스크를 삽입하거나 서로 다른 층간물질을 선택할 수 있다.At this time, the second and third insulating films 3 and 4 are made of a material having a low dielectric constant {low-k; The k value ranges from 2.0 to 2.7. In addition, a hard mask may be inserted into the etch stop layer between the second and third insulating layers 3 and 4, or different interlayer materials may be selected.
상기 제 3 절연막(4) 위에 포지티브 화학증폭형 감광막(5)을 형성한 다음, 엑시머 레이저를 레티클(8)을 통해 조사하여 현상공정을 진행하는 단계이다. 상기 레티클(8)의 하부에는 크롬(Cr) 마스크 패턴(7)이 형성되어 있다. 그리고, 상기 감광막(5)은 공정마진과 최적 패턴뿐 아니라 감광막(5)의 열적 플로우 공정(Resist Flow Process)을 고려하여 감광막(5)의 두께를 결정한다.After the positive chemically amplified photosensitive film 5 is formed on the third insulating film 4, the development process is performed by irradiating an excimer laser through the reticle 8. A chromium (Cr) mask pattern 7 is formed below the reticle 8. The photoresist film 5 determines the thickness of the photoresist film 5 in consideration of a process flow and an optimum pattern as well as a thermal flow process of the photoresist film 5.
도 2d에 도시된 공정은, 도 2c의 현상공정에 의해 감광막 패턴(5)이 형성된 단계이다.The process shown in FIG. 2D is a step in which the photosensitive film pattern 5 is formed by the developing process of FIG. 2C.
도 2e에 도시된 공정은, 상기 감광막 패턴(5)을 마스크로 하여 상기 제 3 절연막(4)을 트렌치 식각하여 트렌치 패턴을 형성한 단계이다.The process shown in FIG. 2E is a step of forming a trench pattern by trench etching the third insulating film 4 using the photoresist pattern 5 as a mask.
도 2f에 도시된 공정은, 도 2e의 구조물 위에 상기 감광막(5)의 유리 온도를 고려하여 감광막을 플로우시켜, 비아홀 형성을 위한 식각장벽이 되도록 하는 스페이서 감광막 패턴(6)을 트렌치 측면에 형성한 단계이다.In the process shown in FIG. 2F, the photoresist film is flowed on the structure of FIG. 2E in consideration of the glass temperature of the photoresist film 5 to form a spacer photoresist pattern 6 on the side of the trench to form an etch barrier for forming a via hole. Step.
도 2g에 도시된 공정은, 상기 스페이서 감광막 패턴(6)을 마스크로하여 상기 제 2 절연막(3)을 건식 식각한 단계이다.The process illustrated in FIG. 2G is a step of dry etching the second insulating layer 3 using the spacer photoresist pattern 6 as a mask.
도 2h에 도시된 공정은, 상기 스페이서 감광막 패턴(6)을 제거하여 다마신 패턴을 형성시킨 단계이다.The process shown in FIG. 2H is a step of forming the damascene pattern by removing the spacer photoresist pattern 6.
다음, 도면에는 도시되어 있지 않으나, 듀얼다마신 패턴형성후 탄탈륨(Ta)과 탄탈륨 나이트라이드(TaN) 등의 구리 확산 방지층(Copper Diffusion BarrierLayer)과 구리를 증착하고 평탄화 공정을 거치면 배선공정이 완성되게 된다.Next, although not shown in the drawing, after forming a dual damascene pattern, a copper diffusion barrier layer such as tantalum (Ta) and tantalum nitride (TaN) and copper are deposited and planarized to complete the wiring process. do.
이상에서 설명한 바와 같이, 본 발명에 의한 반도체 소자의 제조 방법은 노광장비를 한번만 사용하고 감광막의 열적 흐름 공정(Resist Flow Process)을 이용하여 감광막 스페이서 패턴을 완성하고 이를 이용한 듀얼 다마신 패턴을 형성함으로써, 구리 배선 형성 공정을 단순화시킬 수 있고 디바이스의 제조시 원가를 절감할 수 있다.As described above, in the method of manufacturing a semiconductor device according to the present invention, the photoresist spacer pattern is completed by using the exposure equipment only once and using the resistive flow process of the photoresist film, and forming a dual damascene pattern using the same. As a result, the copper wiring forming process can be simplified, and the manufacturing cost of the device can be reduced.
아울러 본 발명의 바람직한 실시예들은 예시의 목적을 위해 개시된 것이며, 당업자라면 본 발명의 사상과 범위 안에서 다양한 수정, 변경, 부가등이 가능할 것이며, 이러한 수정 변경등은 이하의 특허청구범위에 속하는 것으로 보아야 할 것이다.In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to various modifications, changes, additions, etc. within the spirit and scope of the present invention, these modifications and changes should be seen as belonging to the following claims. something to do.
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| US5614765A (en) * | 1995-06-07 | 1997-03-25 | Advanced Micro Devices, Inc. | Self aligned via dual damascene |
| US5893748A (en) * | 1997-02-10 | 1999-04-13 | Advanced Micro Devices, Inc. | Method for producing semiconductor devices with small contacts, vias, or damascene trenches |
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| KR19990081061A (en) * | 1998-04-24 | 1999-11-15 | 윤종용 | Method of forming fine contact hole in semiconductor device |
| KR20010077260A (en) * | 2000-02-01 | 2001-08-17 | 윤종용 | The method of forming bit line of semiconductor memory devices |
| JP2002222872A (en) * | 2001-01-10 | 2002-08-09 | Samsung Electronics Co Ltd | Method of manufacturing cylindrical capacitor for semiconductor device |
| KR20030002238A (en) * | 2001-06-30 | 2003-01-08 | 주식회사 하이닉스반도체 | method of forming dual damascene pattern using photo resist spacer |
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| US5614765A (en) * | 1995-06-07 | 1997-03-25 | Advanced Micro Devices, Inc. | Self aligned via dual damascene |
| US5893748A (en) * | 1997-02-10 | 1999-04-13 | Advanced Micro Devices, Inc. | Method for producing semiconductor devices with small contacts, vias, or damascene trenches |
| KR19990031075A (en) * | 1997-10-08 | 1999-05-06 | 윤종용 | Method for forming contact hole in semiconductor device |
| KR19990081061A (en) * | 1998-04-24 | 1999-11-15 | 윤종용 | Method of forming fine contact hole in semiconductor device |
| KR20010077260A (en) * | 2000-02-01 | 2001-08-17 | 윤종용 | The method of forming bit line of semiconductor memory devices |
| JP2002222872A (en) * | 2001-01-10 | 2002-08-09 | Samsung Electronics Co Ltd | Method of manufacturing cylindrical capacitor for semiconductor device |
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