KR20040004105A - 집적 회로, 집적 회로의 제조 프로세스 및 집적 회로에대한 테스트 프로세스 - Google Patents

집적 회로, 집적 회로의 제조 프로세스 및 집적 회로에대한 테스트 프로세스 Download PDF

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Publication number
KR20040004105A
KR20040004105A KR1020030044101A KR20030044101A KR20040004105A KR 20040004105 A KR20040004105 A KR 20040004105A KR 1020030044101 A KR1020030044101 A KR 1020030044101A KR 20030044101 A KR20030044101 A KR 20030044101A KR 20040004105 A KR20040004105 A KR 20040004105A
Authority
KR
South Korea
Prior art keywords
integrated circuit
memory
test
information
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
KR1020030044101A
Other languages
English (en)
Korean (ko)
Inventor
맥아담스휴피
그레이스제임스더블유
Original Assignee
애질런트 테크놀로지스, 인크.
텍사스 인스트루먼츠 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 애질런트 테크놀로지스, 인크., 텍사스 인스트루먼츠 인코포레이티드 filed Critical 애질런트 테크놀로지스, 인크.
Publication of KR20040004105A publication Critical patent/KR20040004105A/ko
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44—Indication or identification of errors, e.g. for repair
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/20—Initialising; Data preset; Chip identification
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C2029/4402—Internal storage of test result, quality data, chip identification, repair information

Landscapes

  • Tests Of Electronic Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)
KR1020030044101A 2002-07-02 2003-07-01 집적 회로, 집적 회로의 제조 프로세스 및 집적 회로에대한 테스트 프로세스 Ceased KR20040004105A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/190,408 2002-07-02
US10/190,408 US6952623B2 (en) 2002-07-02 2002-07-02 Permanent chip ID using FeRAM

Publications (1)

Publication Number Publication Date
KR20040004105A true KR20040004105A (ko) 2004-01-13

Family

ID=29999875

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020030044101A Ceased KR20040004105A (ko) 2002-07-02 2003-07-01 집적 회로, 집적 회로의 제조 프로세스 및 집적 회로에대한 테스트 프로세스

Country Status (4)

Country Link
US (1) US6952623B2 (https=)
JP (1) JP2004040103A (https=)
KR (1) KR20040004105A (https=)
DE (1) DE10318183A1 (https=)

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US7149931B2 (en) * 2004-02-25 2006-12-12 Realtek Semiconductor Corp. Method and apparatus for providing fault tolerance to memory
US20050210205A1 (en) * 2004-03-17 2005-09-22 Chang-Lien Wu Method for employing memory with defective sections
DE102004047813A1 (de) * 2004-09-29 2006-03-30 Infineon Technologies Ag Halbleiterbaustein mit einer Umlenkschaltung
CN101040290A (zh) * 2004-10-15 2007-09-19 应用材料股份有限公司 半导体组件的晶粒跟踪装置及其测试设备
US20060133607A1 (en) * 2004-12-22 2006-06-22 Seagate Technology Llc Apparatus and method for generating a secret key
WO2006134783A1 (ja) * 2005-06-15 2006-12-21 Murata Kikai Kabushiki Kaisha 巻き糸パッケージの巻取り管および巻き糸パッケージの管理装置
US20070162713A1 (en) * 2006-01-09 2007-07-12 Josef Schnell Memory having status register read function
JP2008159813A (ja) * 2006-12-22 2008-07-10 Sharp Corp 自らのチップ識別情報の読み取りを行える情報出力装置、チップ識別情報記録部を有する半導体集積回路、およびチップ識別情報の読み出し方法
JP2009021398A (ja) * 2007-07-12 2009-01-29 Seiko Epson Corp 半導体チップ及び半導体チップへのプロセス・デバイス情報書き込み方法
WO2009075675A1 (en) * 2007-12-10 2009-06-18 Agere Systems Inc. Chip identification using top metal layer
US20090146144A1 (en) * 2007-12-10 2009-06-11 Broadcom Corporation Method and system supporting production of a semiconductor device using a plurality of fabrication processes
US8966660B2 (en) * 2008-08-07 2015-02-24 William Marsh Rice University Methods and systems of digital rights management for integrated circuits
US8170857B2 (en) * 2008-11-26 2012-05-01 International Business Machines Corporation In-situ design method and system for improved memory yield
US8059478B2 (en) * 2008-12-04 2011-11-15 Kovio, Inc. Low cost testing and sorting for integrated circuits
TWI560456B (en) * 2009-03-20 2016-12-01 Bravechips Microelectronics Method of parallel ic test and wafer containing same function dies under test and ic chips containing same function blocks under test
TW201519300A (zh) * 2013-11-08 2015-05-16 日月光半導體製造股份有限公司 半導體製程
JP2015114814A (ja) * 2013-12-11 2015-06-22 株式会社デンソー 半導体装置の製品履歴管理方法
CN104678287B (zh) * 2015-01-30 2018-10-16 上海华岭集成电路技术股份有限公司 芯片uid映射写入方法
US9940486B2 (en) * 2015-02-23 2018-04-10 Cisco Technology, Inc. Detection of hardware tampering
US10237063B2 (en) * 2016-12-13 2019-03-19 Nxp B.V. Distributed cryptographic key insertion and key delivery
US10685918B2 (en) 2018-08-28 2020-06-16 Semiconductor Components Industries, Llc Process variation as die level traceability
CN114289339B (zh) * 2021-12-10 2023-09-26 郑州信大捷安信息技术股份有限公司 一种芯片自动化检测方法和装置
US12190977B2 (en) * 2023-03-29 2025-01-07 Nanya Technology Corporation Memory test system and memory test method

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100781431B1 (ko) * 2005-07-07 2007-12-03 인피니언 테크놀로지스 아게 반도체 웨이퍼 칩을 테스트하고 개별적으로 구성하는 방법및 시스템

Also Published As

Publication number Publication date
DE10318183A1 (de) 2004-01-29
US6952623B2 (en) 2005-10-04
US20040006404A1 (en) 2004-01-08
JP2004040103A (ja) 2004-02-05

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