JP2004040103A - ＦｅＲＡＭを用いた永久的チップＩＤ - Google Patents

ＦｅＲＡＭを用いた永久的チップＩＤ Download PDF

Info

Publication number
JP2004040103A
JP2004040103A JP2003186753A JP2003186753A JP2004040103A JP 2004040103 A JP2004040103 A JP 2004040103A JP 2003186753 A JP2003186753 A JP 2003186753A JP 2003186753 A JP2003186753 A JP 2003186753A JP 2004040103 A JP2004040103 A JP 2004040103A
Authority
JP
Japan
Prior art keywords
integrated circuit
memory
information
chip
test
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2003186753A
Other languages
English (en)
Japanese (ja)
Other versions
JP2004040103A5 (https=
Inventor
Hugh P Mcadams
ヒュー・ピー・マクアダムス
James W Grace
ジェイムス・ダブリュー・グレース
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Agilent Technologies Inc
Texas Instruments Inc
Original Assignee
Agilent Technologies Inc
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agilent Technologies Inc, Texas Instruments Inc filed Critical Agilent Technologies Inc
Publication of JP2004040103A publication Critical patent/JP2004040103A/ja
Publication of JP2004040103A5 publication Critical patent/JP2004040103A5/ja
Pending legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44—Indication or identification of errors, e.g. for repair
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/20—Initialising; Data preset; Chip identification
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C2029/4402—Internal storage of test result, quality data, chip identification, repair information

Landscapes

  • Tests Of Electronic Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)
JP2003186753A 2002-07-02 2003-06-30 ＦｅＲＡＭを用いた永久的チップＩＤ Pending JP2004040103A (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/190,408 US6952623B2 (en) 2002-07-02 2002-07-02 Permanent chip ID using FeRAM

Publications (2)

Publication Number Publication Date
JP2004040103A true JP2004040103A (ja) 2004-02-05
JP2004040103A5 JP2004040103A5 (https=) 2006-08-03

Family

ID=29999875

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003186753A Pending JP2004040103A (ja) 2002-07-02 2003-06-30 ＦｅＲＡＭを用いた永久的チップＩＤ

Country Status (4)

Country Link
US (1) US6952623B2 (https=)
JP (1) JP2004040103A (https=)
KR (1) KR20040004105A (https=)
DE (1) DE10318183A1 (https=)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008159813A (ja) * 2006-12-22 2008-07-10 Sharp Corp 自らのチップ識別情報の読み取りを行える情報出力装置、チップ識別情報記録部を有する半導体集積回路、およびチップ識別情報の読み出し方法
JPWO2006134783A1 (ja) * 2005-06-15 2009-01-08 村田機械株式会社 巻き糸パッケージの巻取り管および巻き糸パッケージの管理装置
JP2009021398A (ja) * 2007-07-12 2009-01-29 Seiko Epson Corp 半導体チップ及び半導体チップへのプロセス・デバイス情報書き込み方法
JP2010223960A (ja) * 2009-03-20 2010-10-07 Shanghai Xinhao (Bravechips) Micro Electronics Co Ltd 集積回路の並行検査の方法、装置及びシステム
JP2015114814A (ja) * 2013-12-11 2015-06-22 株式会社デンソー 半導体装置の製品履歴管理方法

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7668702B2 (en) * 2002-07-19 2010-02-23 Applied Materials, Inc. Method, system and medium for controlling manufacturing process using adaptive models based on empirical data
US7496817B2 (en) * 2004-02-20 2009-02-24 Realtek Semiconductor Corp. Method for determining integrity of memory
US7149931B2 (en) * 2004-02-25 2006-12-12 Realtek Semiconductor Corp. Method and apparatus for providing fault tolerance to memory
US20050210205A1 (en) * 2004-03-17 2005-09-22 Chang-Lien Wu Method for employing memory with defective sections
DE102004047813A1 (de) * 2004-09-29 2006-03-30 Infineon Technologies Ag Halbleiterbaustein mit einer Umlenkschaltung
CN101040290A (zh) * 2004-10-15 2007-09-19 应用材料股份有限公司 半导体组件的晶粒跟踪装置及其测试设备
US20060133607A1 (en) * 2004-12-22 2006-06-22 Seagate Technology Llc Apparatus and method for generating a secret key
US7299388B2 (en) * 2005-07-07 2007-11-20 Infineon Technologies, Ag Method and apparatus for selectively accessing and configuring individual chips of a semi-conductor wafer
US20070162713A1 (en) * 2006-01-09 2007-07-12 Josef Schnell Memory having status register read function
WO2009075675A1 (en) * 2007-12-10 2009-06-18 Agere Systems Inc. Chip identification using top metal layer
US20090146144A1 (en) * 2007-12-10 2009-06-11 Broadcom Corporation Method and system supporting production of a semiconductor device using a plurality of fabrication processes
US8966660B2 (en) * 2008-08-07 2015-02-24 William Marsh Rice University Methods and systems of digital rights management for integrated circuits
US8170857B2 (en) * 2008-11-26 2012-05-01 International Business Machines Corporation In-situ design method and system for improved memory yield
US8059478B2 (en) * 2008-12-04 2011-11-15 Kovio, Inc. Low cost testing and sorting for integrated circuits
TW201519300A (zh) * 2013-11-08 2015-05-16 日月光半導體製造股份有限公司 半導體製程
CN104678287B (zh) * 2015-01-30 2018-10-16 上海华岭集成电路技术股份有限公司 芯片uid映射写入方法
US9940486B2 (en) * 2015-02-23 2018-04-10 Cisco Technology, Inc. Detection of hardware tampering
US10237063B2 (en) * 2016-12-13 2019-03-19 Nxp B.V. Distributed cryptographic key insertion and key delivery
US10685918B2 (en) 2018-08-28 2020-06-16 Semiconductor Components Industries, Llc Process variation as die level traceability
CN114289339B (zh) * 2021-12-10 2023-09-26 郑州信大捷安信息技术股份有限公司 一种芯片自动化检测方法和装置
US12190977B2 (en) * 2023-03-29 2025-01-07 Nanya Technology Corporation Memory test system and memory test method

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6053043A (ja) * 1983-09-02 1985-03-26 Toshiba Corp 半導体集積回路装置
JPH03269900A (ja) * 1990-03-19 1991-12-02 Sharp Corp 半導体集積回路
JPH05243359A (ja) * 1990-04-16 1993-09-21 Natl Semiconductor Corp <Ns> チップダイ用強誘電コンデンサテスト構成体
JPH08162862A (ja) * 1994-12-08 1996-06-21 Hitachi Ltd 差動増幅器のオフセット電圧測定方法およびそれを用いた半導体集積回路装置の製造方法、半導体集積回路装置
JP2000208567A (ja) * 1999-01-18 2000-07-28 Nec Corp 半導体集積回路及びそのテスト方法

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5254482A (en) * 1990-04-16 1993-10-19 National Semiconductor Corporation Ferroelectric capacitor test structure for chip die
JPH0682325B2 (ja) * 1990-05-29 1994-10-19 株式会社東芝 情報処理装置のテスト容易化回路
US6194738B1 (en) * 1996-06-13 2001-02-27 Micron Technology, Inc. Method and apparatus for storage of test results within an integrated circuit
US5862151A (en) * 1997-01-23 1999-01-19 Unisys Corporation Array self-test fault tolerant programmable threshold algorithm
US5915231A (en) * 1997-02-26 1999-06-22 Micron Technology, Inc. Method in an integrated circuit (IC) manufacturing process for identifying and redirecting IC's mis-processed during their manufacture
US5856923A (en) * 1997-03-24 1999-01-05 Micron Technology, Inc. Method for continuous, non lot-based integrated circuit manufacturing
US5907492A (en) * 1997-06-06 1999-05-25 Micron Technology, Inc. Method for using data regarding manufacturing procedures integrated circuits (IC's) have undergone, such as repairs, to select procedures the IC's will undergo, such as additional repairs
US5764655A (en) * 1997-07-02 1998-06-09 International Business Machines Corporation Built in self test with memory
US6446017B1 (en) * 1997-08-21 2002-09-03 Micron Technology, Inc. Method and system for tracking manufacturing data for integrated circuit parts
US6085334A (en) * 1998-04-17 2000-07-04 Motorola, Inc. Method and apparatus for testing an integrated memory device
KR100333720B1 (ko) * 1998-06-30 2002-06-20 박종섭 강유전체메모리소자의리던던시회로
US6067262A (en) * 1998-12-11 2000-05-23 Lsi Logic Corporation Redundancy analysis for embedded memories with built-in self test and built-in self repair
US6161213A (en) * 1999-02-17 2000-12-12 Icid, Llc System for providing an integrated circuit with a unique identification
JP4183333B2 (ja) * 1999-03-23 2008-11-19 株式会社 沖マイクロデザイン 半導体集積回路およびその試験方法
US6456554B1 (en) * 1999-10-19 2002-09-24 Texas Instruments Incorporated Chip identifier and method of fabrication
JP2001208798A (ja) * 2000-01-26 2001-08-03 Mitsubishi Electric Corp 半導体回路のテスト方法および装置
JP3980827B2 (ja) * 2000-03-10 2007-09-26 株式会社ルネサステクノロジ 半導体集積回路装置および製造方法
JP2001291385A (ja) * 2000-04-05 2001-10-19 Nec Corp 半導体記憶装置並びにその試験装置および試験方法
JP3775716B2 (ja) * 2000-05-25 2006-05-17 シャープ株式会社 強誘電体型記憶装置およびそのテスト方法
DE10102432B4 (de) * 2001-01-19 2005-09-22 Infineon Technologies Ag Testschaltung zur analogen Messung von Bitleitungssignalen ferroelektrischer Speicherzellen
DE10127421C2 (de) * 2001-06-06 2003-06-05 Infineon Technologies Ag Verfahren zum Erkennen und zum Ersetzen von fehlerhaften Speicherzellen in einem Speicher
US20030018937A1 (en) * 2001-07-18 2003-01-23 Athavale Atul S. Method and apparatus for efficient self-test of voltage and current level testing
US6590799B1 (en) * 2002-05-29 2003-07-08 Agilent Technologies, Inc. On-chip charge distribution measurement circuit

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6053043A (ja) * 1983-09-02 1985-03-26 Toshiba Corp 半導体集積回路装置
JPH03269900A (ja) * 1990-03-19 1991-12-02 Sharp Corp 半導体集積回路
JPH05243359A (ja) * 1990-04-16 1993-09-21 Natl Semiconductor Corp <Ns> チップダイ用強誘電コンデンサテスト構成体
JPH08162862A (ja) * 1994-12-08 1996-06-21 Hitachi Ltd 差動増幅器のオフセット電圧測定方法およびそれを用いた半導体集積回路装置の製造方法、半導体集積回路装置
JP2000208567A (ja) * 1999-01-18 2000-07-28 Nec Corp 半導体集積回路及びそのテスト方法

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2006134783A1 (ja) * 2005-06-15 2009-01-08 村田機械株式会社 巻き糸パッケージの巻取り管および巻き糸パッケージの管理装置
JP2008159813A (ja) * 2006-12-22 2008-07-10 Sharp Corp 自らのチップ識別情報の読み取りを行える情報出力装置、チップ識別情報記録部を有する半導体集積回路、およびチップ識別情報の読み出し方法
JP2009021398A (ja) * 2007-07-12 2009-01-29 Seiko Epson Corp 半導体チップ及び半導体チップへのプロセス・デバイス情報書き込み方法
JP2010223960A (ja) * 2009-03-20 2010-10-07 Shanghai Xinhao (Bravechips) Micro Electronics Co Ltd 集積回路の並行検査の方法、装置及びシステム
JP2015114814A (ja) * 2013-12-11 2015-06-22 株式会社デンソー 半導体装置の製品履歴管理方法

Also Published As

Publication number Publication date
DE10318183A1 (de) 2004-01-29
KR20040004105A (ko) 2004-01-13
US6952623B2 (en) 2005-10-04
US20040006404A1 (en) 2004-01-08

Similar Documents

Publication Publication Date Title
JP2004040103A (ja) ＦｅＲＡＭを用いた永久的チップＩＤ
US7890819B2 (en) Method and apparatus for storing failing part locations in a module
TWI467591B (zh) 於非揮發記憶體系統中損壞區塊隔離的方法及其相關非揮發記憶體器件
US8482997B2 (en) Method of manufacturing non-volatile memory module
US7694196B2 (en) Self-diagnostic scheme for detecting errors
KR100272712B1 (ko) 간단한 검사용 배선을 갖고 짧은 시간에 검사될 수 있는 반도체 웨이퍼상의 반도체 장치
US6934205B1 (en) Bist for parallel testing of on chip memory
US5913020A (en) Method for using fuse identification codes for masking bad bits on single in-line memory modules
US7454662B2 (en) Integrated memory having a circuit for testing the operation of the integrated memory, and method for operating the integrated memory
TWI855299B (zh) 積體電路及其啟動方法
US5721741A (en) Memory test system
KR100399449B1 (ko) 메모리 셀 장치 및 메모리 셀의 기능 테스트 방법
US6961880B2 (en) Recording test information to identify memory cell errors
US7496817B2 (en) Method for determining integrity of memory
JPH07335000A (ja) 不揮発性メモリ
US20250391494A1 (en) Apparatus including internal capacity measurement and associated methods
KR101126944B1 (ko) 반도체 장치
US11164649B1 (en) Test method for memory device
TWI298884B (en) Methods and systmes for tracing back positions of memory chips on an origin wafer thereof
KR100763357B1 (ko) 테스트하는 동안의 메모리 중복성 가능화
CN121096403A (zh) 桥接集成芯片、dram和soc系统
CN119847840A (zh) Hsa引脚电阻值选择方法、装置和计算机可读存储介质
JPH0467645A (ja) バーンイン装置
CN117992288A (zh) 测试包括在存储装置中的存储控制器的方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20060616

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20060616

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20090821

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20091117

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20100427