KR20030015760A - 반도체패키지 - Google Patents
반도체패키지 Download PDFInfo
- Publication number
- KR20030015760A KR20030015760A KR1020010049657A KR20010049657A KR20030015760A KR 20030015760 A KR20030015760 A KR 20030015760A KR 1020010049657 A KR1020010049657 A KR 1020010049657A KR 20010049657 A KR20010049657 A KR 20010049657A KR 20030015760 A KR20030015760 A KR 20030015760A
- Authority
- KR
- South Korea
- Prior art keywords
- semiconductor package
- stiffener
- substrate
- semiconductor chip
- hole
- Prior art date
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
Claims (4)
- 상,하면에 회로패턴이 형성된 대략 판상의 섭스트레이트와, 상기 섭스트레이트 상면의 중앙에 도전성범프에 의해 상기 회로패턴에 연결된 반도체칩과, 상기 반도체칩의 외주연에 접착된 스티프너와, 상기 반도체칩 및 스티프너 상부에 접착된 히트싱크와, 상기 섭스트레이트 하면의 회로패턴에 융착된 다수의 도전성볼로 이루어진 반도체패키지에 있어서,상기 스티프너는 다수의 통공이 형성되어 있고, 상기 통공에는 수동소자가 위치되어 상기 섭스트레이트의 회로패턴에 전기적으로 연결된 것을 특징으로 하는 반도체패키지.
- 제1항에 있어서, 상기 스티프너는 평면상 중앙에 반도체칩이 위치될 수 있도록 제1통공이 형성되어 있고, 상기 제1통공의 외주연에는 수동소자가 위치될 수 있도록 다수의 제2통공이 어레이(Array)된 것을 특징으로 하는 반도체패키지.
- 제1항에 있어서, 상기 스티프너는 평면상 중앙에 반도체칩이 위치될 수 있도록 제1통공이 형성되어 있고, 상기 제1통공의 외주연에는 수동소자가 위치될 수 있도록 각 변을 따라 사다리꼴의 제2통공이 형성된 것을 특징으로 하는 반도체패키지.
- 제1항 내지 제3항중 어느 한 항에 있어서, 상기 스티프너의 통공 또는 제2통공에는 글럽탑(Glop Top)이 충진된 것을 특징으로 하는 반도체패키지.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020010049657A KR100779345B1 (ko) | 2001-08-17 | 2001-08-17 | 반도체패키지 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020010049657A KR100779345B1 (ko) | 2001-08-17 | 2001-08-17 | 반도체패키지 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20030015760A true KR20030015760A (ko) | 2003-02-25 |
KR100779345B1 KR100779345B1 (ko) | 2007-11-23 |
Family
ID=27719601
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020010049657A KR100779345B1 (ko) | 2001-08-17 | 2001-08-17 | 반도체패키지 |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR100779345B1 (ko) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100836645B1 (ko) * | 2007-03-06 | 2008-06-10 | 삼성전기주식회사 | 전자 패키지 및 그 제조방법 |
US7902664B2 (en) | 2006-07-28 | 2011-03-08 | Samsung Electronics Co., Ltd. | Semiconductor package having passive component and semiconductor memory module including the same |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20140115668A (ko) | 2013-03-21 | 2014-10-01 | 삼성전자주식회사 | 방열판과 수동 소자를 갖는 반도체 패키지 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0722728A (ja) * | 1993-07-06 | 1995-01-24 | Ibiden Co Ltd | 電子部品搭載用基板 |
JP3078773B2 (ja) * | 1997-11-14 | 2000-08-21 | 松下電器産業株式会社 | 電子部品およびその製造方法 |
JPH11233711A (ja) * | 1998-02-06 | 1999-08-27 | Hitachi Ltd | 半導体装置およびその製造方法 |
JPH11340387A (ja) * | 1998-05-29 | 1999-12-10 | Hitachi Ltd | 半導体装置及びその実装方法並びに電子装置 |
JP2001267473A (ja) * | 2000-03-17 | 2001-09-28 | Hitachi Ltd | 半導体装置およびその製造方法 |
-
2001
- 2001-08-17 KR KR1020010049657A patent/KR100779345B1/ko active IP Right Grant
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7902664B2 (en) | 2006-07-28 | 2011-03-08 | Samsung Electronics Co., Ltd. | Semiconductor package having passive component and semiconductor memory module including the same |
KR100836645B1 (ko) * | 2007-03-06 | 2008-06-10 | 삼성전기주식회사 | 전자 패키지 및 그 제조방법 |
Also Published As
Publication number | Publication date |
---|---|
KR100779345B1 (ko) | 2007-11-23 |
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