KR20010080635A - 텅스텐 실리사이드막을 형성하여 금속-절연막-반도체형트랜지스터를 제조하는 방법 - Google Patents

텅스텐 실리사이드막을 형성하여 금속-절연막-반도체형트랜지스터를 제조하는 방법 Download PDF

Info

Publication number
KR20010080635A
KR20010080635A KR1020017006766A KR20017006766A KR20010080635A KR 20010080635 A KR20010080635 A KR 20010080635A KR 1020017006766 A KR1020017006766 A KR 1020017006766A KR 20017006766 A KR20017006766 A KR 20017006766A KR 20010080635 A KR20010080635 A KR 20010080635A
Authority
KR
South Korea
Prior art keywords
film
forming
tungsten silicide
silicon
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
KR1020017006766A
Other languages
English (en)
Korean (ko)
Inventor
마나부 야마자끼
유지 마에다
야스유끼 가네코
이치로 가와이
Original Assignee
조셉 제이. 스위니
어플라이드 머티어리얼스, 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 조셉 제이. 스위니, 어플라이드 머티어리얼스, 인코포레이티드 filed Critical 조셉 제이. 스위니
Publication of KR20010080635A publication Critical patent/KR20010080635A/ko
Ceased legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/24Alloying of impurity materials, e.g. doping materials, electrode materials, with a semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/268Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
    • H01L21/2686Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation using incoherent radiation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28052Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/60Electrodes characterised by their materials
    • H10D64/66Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/661Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
    • H10D64/662Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures
    • H10D64/663Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Optics & Photonics (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Chemical Vapour Deposition (AREA)
KR1020017006766A 1999-09-30 2000-09-29 텅스텐 실리사이드막을 형성하여 금속-절연막-반도체형트랜지스터를 제조하는 방법 Ceased KR20010080635A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP27960999A JP2001110750A (ja) 1999-09-30 1999-09-30 タングステンシリサイド膜を形成する方法、および金属−絶縁膜−半導体型トランジスタを製造する方法
JP1999-279609 1999-09-30
PCT/JP2000/006791 WO2001024238A1 (fr) 1999-09-30 2000-09-29 Procede de formation de films de siliciure de tungstene et procede de fabrication de transistors metal-isolant-semi-conducteur

Publications (1)

Publication Number Publication Date
KR20010080635A true KR20010080635A (ko) 2001-08-22

Family

ID=17613378

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020017006766A Ceased KR20010080635A (ko) 1999-09-30 2000-09-29 텅스텐 실리사이드막을 형성하여 금속-절연막-반도체형트랜지스터를 제조하는 방법

Country Status (5)

Country Link
EP (1) EP1156517A1 (enExample)
JP (1) JP2001110750A (enExample)
KR (1) KR20010080635A (enExample)
TW (1) TW469517B (enExample)
WO (1) WO2001024238A1 (enExample)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100669141B1 (ko) * 2005-01-17 2007-01-15 삼성전자주식회사 오믹막 및 이의 형성 방법, 오믹막을 포함하는 반도체장치 및 이의 제조 방법
KR100680969B1 (ko) * 2005-08-18 2007-02-09 주식회사 하이닉스반도체 텅스텐실리사이드 박막 형성방법
KR101035738B1 (ko) * 2011-02-24 2011-05-20 주식회사 문라이트 보행자 및 자전거 도로용 조명기구
US9685527B2 (en) 2015-02-17 2017-06-20 Samsung Electronics Co., Ltd. Methods of forming metal silicide layers including dopant segregation

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002044437A2 (en) * 2000-11-02 2002-06-06 Composite Tool Company, Inc. High strength alloys and methods for making same
TWI395254B (zh) * 2006-01-25 2013-05-01 Air Water Inc Film forming device
TWI341012B (en) 2007-09-03 2011-04-21 Macronix Int Co Ltd Methods of forming nitride read only memory and word lines thereof
JP2011258811A (ja) * 2010-06-10 2011-12-22 Ulvac Japan Ltd 半導体装置の製造方法
JP2017022377A (ja) 2015-07-14 2017-01-26 株式会社半導体エネルギー研究所 半導体装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2657306B2 (ja) * 1988-07-29 1997-09-24 東京エレクトロン株式会社 金属シリサイド膜の形成方法
JPH06216066A (ja) * 1993-01-14 1994-08-05 Fujitsu Ltd 半導体装置の製造方法
EP0704551B1 (en) * 1994-09-27 2000-09-06 Applied Materials, Inc. Method of processing a substrate in a vacuum processing chamber
EP0746027A3 (en) * 1995-05-03 1998-04-01 Applied Materials, Inc. Polysilicon/tungsten silicide multilayer composite formed on an integrated circuit structure, and improved method of making same
JPH0917998A (ja) * 1995-06-28 1997-01-17 Sony Corp Mosトランジスタの製造方法

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100669141B1 (ko) * 2005-01-17 2007-01-15 삼성전자주식회사 오믹막 및 이의 형성 방법, 오믹막을 포함하는 반도체장치 및 이의 제조 방법
US7544597B2 (en) 2005-01-17 2009-06-09 Samsung Electronics Co., Ltd. Method of forming a semiconductor device including an ohmic layer
US7875939B2 (en) 2005-01-17 2011-01-25 Samsung Electronics Co., Ltd. Semiconductor device including an ohmic layer
KR100680969B1 (ko) * 2005-08-18 2007-02-09 주식회사 하이닉스반도체 텅스텐실리사이드 박막 형성방법
KR101035738B1 (ko) * 2011-02-24 2011-05-20 주식회사 문라이트 보행자 및 자전거 도로용 조명기구
US9685527B2 (en) 2015-02-17 2017-06-20 Samsung Electronics Co., Ltd. Methods of forming metal silicide layers including dopant segregation

Also Published As

Publication number Publication date
EP1156517A1 (en) 2001-11-21
WO2001024238A1 (fr) 2001-04-05
TW469517B (en) 2001-12-21
JP2001110750A (ja) 2001-04-20

Similar Documents

Publication Publication Date Title
US6380014B1 (en) Manufacture method of semiconductor device with suppressed impurity diffusion from gate electrode
US6258690B1 (en) Method of manufacturing semiconductor device
WO2003060184A2 (en) Method and apparatus for forming silicon containing films
JPH04226026A (ja) 半導体装置の製造方法
JPH11224947A (ja) 半導体装置およびその製造方法
WO2001041544A2 (en) Deposition of gate stacks including silicon germanium layers
KR100192017B1 (ko) 반도체 장치의 제조방법
KR20010080635A (ko) 텅스텐 실리사이드막을 형성하여 금속-절연막-반도체형트랜지스터를 제조하는 방법
JP4441109B2 (ja) 半導体装置の製造方法
JP3635843B2 (ja) 膜積層構造及びその形成方法
US6635938B1 (en) Semiconductor device and manufacturing method thereof
US6632721B1 (en) Method of manufacturing semiconductor devices having capacitors with electrode including hemispherical grains
JP2000058483A (ja) 半導体装置の製造方法
US5882962A (en) Method of fabricating MOS transistor having a P+ -polysilicon gate
JP2003282873A (ja) 半導体装置およびその製造方法
JP3156590B2 (ja) 半導体装置及びその製造方法
JP2005064032A (ja) 半導体装置及びその製造方法
US20050285206A1 (en) Semiconductor device and manufacturing method thereof
US6403455B1 (en) Methods of fabricating a memory device
US8115263B2 (en) Laminated silicon gate electrode
CN1159076A (zh) 半导体器件的平整方法
US6180539B1 (en) Method of forming an inter-poly oxide layer
US6323098B1 (en) Manufacturing method of a semiconductor device
JPH04336466A (ja) 半導体装置の製造方法
KR100296960B1 (ko) 반도체소자의폴리실리콘막형성방법

Legal Events

Date Code Title Description
PA0105 International application

Patent event date: 20010530

Patent event code: PA01051R01D

Comment text: International Patent Application

A201 Request for examination
PA0201 Request for examination

Patent event code: PA02012R01D

Patent event date: 20010531

Comment text: Request for Examination of Application

PG1501 Laying open of application
E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

Comment text: Notification of reason for refusal

Patent event date: 20030523

Patent event code: PE09021S01D

E601 Decision to refuse application
PE0601 Decision on rejection of patent

Patent event date: 20030807

Comment text: Decision to Refuse Application

Patent event code: PE06012S01D

Patent event date: 20030523

Comment text: Notification of reason for refusal

Patent event code: PE06011S01I