KR20010037447A - Apparatus for selecting network synchronous clock signal of switching system - Google Patents

Abstract

PURPOSE: A device for selecting a clock signal synchronized with net of a switching system is provided to select a clock signal synchronized with an outer net by composing a circuit simply with informing the clock signal to a main control card and controlling the output of the buffer enable clock signal. CONSTITUTION: A device for selecting a clock signal synchronized with net of a switching system includes a digital trunk card(100) and a main control card(200). The digital trunk card(100) includes a synchronous signal generating portion(115) generating the synchronous signals(S8K-SLOT) of appropriate slot line cards and clock signal output buffers(110) controlling the output of the clock signal and an interrupt generating portions(120). The main control card(200) includes a PLL logic portion(230), a processor(210) and an interrupt decoder(220). The interrupt generating portion(120) informs the interrupt signals(INT-SLOT) of the appropriate lines to the interrupt decoder(220) and the interrupt decoder(220) decodes the interrupt signals(INT-SLOT) and outputs them to the processor(210) and the processor(210) permits the enable signal to the clock signal output buffer(110) and the clock signal output buffer(110) outputs the reference clock signal(Ref-8K) synchronized by the enable signal of the processor(210) to the PLL logic portion(230).

Description

Network Synchronous Clock Signal Selector in Switching System {APPARATUS FOR SELECTING NETWORK SYNCHRONOUS CLOCK SIGNAL OF SWITCHING SYSTEM}

The present invention relates to an apparatus for selecting a network synchronization clock signal of an exchange system, and more particularly, by mounting an output buffer for a clock signal to inform the main control card of the clock signal as an interrupt and outputting a buffer enable clock signal. The present invention relates to a network synchronous clock signal selection device of an exchange system capable of selecting a clock signal synchronized with an external network by a simple circuit configuration.

As is well known to those skilled in the art, when using a digital trunk as an external trunk trunk in a switching system, it is important to synchronize with an external network for the accuracy of voice and data exchange. It is necessary to generate various clock signals needed by the exchange system and supply them to all subscriber cards.

1 and 2, the system clock required in one practical embodiment of the prior art is 4.096 MHz in PLL (PLL) logic 10 with an 8.192 MHz clock oscillator 1; A clock signal and F OI are generated and input to the system engine STL7065 20, and the clock signal of the 16.384 MHz oscillator 22 is input to a processor (not shown) and the system engine 20. The system engine 20 receives the clock signals and generates 4.096 MHz, 2.048 MHz, 1 KHz, FSX, etc. required by the exchange system and supplies them to the line cards 30 mounted in each slot.

In FIG. 2, if a digital trunk card is mounted in an exchange system and connected to an external network to activate a line, the clock signal S8K synchronized with the external network with the ACTIVE signal from the line card 30 of the corresponding slot. ) Is output. The active signal is output from the line active signal generator 32 and the synchronous clock signal S8K is output from the synchronous signal generator 33.

As described above, the active signal output from the active signal generator 32 is first input to the PRIORITY encoder 41, and the control signal encoded according to the priority is output, and the control signal is again multiplexer 42. The clock signal (S8K) generated from the card connected to the external network is selected as the reference clock signal (Ref-8K) of the switching system from among the clock signals (S8K) generated from each slot as the input signal. The clock signal is divided into quarters to be input signals to the PLL logic 10 of the system.

If the digital trunk is not mounted, the active signal and the synchronous clock signal S8K are not generated. Therefore, the clock signal 8K, which is frequency-divided by the 16.384 MHz oscillator 22, is output as the reference clock signal 8K as it is. It is input to the logic 10.

However, in the prior art as described above, since the line activation signal must be used to select the clock signal 8K synchronized with the external network, a complicated circuit configuration for this is required. Due to such a complicated circuit configuration, there have been various problems such as complicated device configuration of the exchange system and additional manufacturing cost.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and is equipped with an output buffer for a clock signal to inform the main control card of the clock signal as an interrupt and to interrupt the output of the buffer enable clock signal. It is an object of the present invention to provide a network synchronization clock signal selection device of a switching system that allows a clock signal synchronized with an external network to be selected by a circuit configuration.

1 and 2 is a schematic configuration diagram of a network synchronization clock signal selection device of a switching system according to the prior art,

3 is a block diagram of a network synchronization clock signal selection device of an exchange system according to the present invention.

<Description of the code used in the main part of the drawing>

100: digital trunk card 110: clock signal output buffer

115: synchronization signal generator 120: interrupt generator

200: main control card 210: processor

220: interrupt decoder 230: PLL logic unit

In order to achieve the above object, the apparatus for selecting a network synchronous clock signal of an exchange system according to the present invention is a device for selecting a network synchronous clock signal of an exchange system, comprising: a synchronization signal generator for generating a synchronized clock signal and the clock signal; A digital trunk card having a clock signal output buffer for interrupting the output of said output and an interrupt generating means; A main control card having a PLL logic section, a processor section, and an interrupt decoder section; The interrupt generating means informs the interrupt decoder of an interrupt signal of a corresponding line when the line of the switching system is activated, and the interrupt decoder decodes the interrupt signal and outputs the interrupt signal to the processor, wherein the processor decodes the interrupt decoder. A predetermined enable signal is applied to the clock signal output buffer with reference to an output signal, and the clock signal output buffer is configured to output a clock signal synchronized with the enable signal of the processor unit to the PL logic unit. It has its features.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the network synchronization clock signal selection device of the switching system according to the present invention.

3 is a block diagram of a network synchronization clock signal selection device of an exchange system according to the present invention.

Referring to FIG. 3, the apparatus for selecting a network synchronous clock signal of the switching system of the present invention is configured to output an output of the clock signal and a synchronization signal generator 115 for generating a synchronized clock signal S8K-SLOT of a corresponding slot line card. A digital trunk card 100 having an intermittent clock signal output buffer 110 and an interrupt generator 120; And a main control card 200 having a PLL logic unit 230, a processor 210, and an interrupt decoder 220. Here, the interrupt generator 120 informs the interrupt decoder 220 of the interrupt signal (INT-SLOT) of the corresponding line when the line of the switching system is activated, and the interrupt decoder 220 decodes the interrupt signal (INT-SLOT). The controller 210 outputs the signal to the processor 210, and the processor 210 applies a predetermined enable signal to the clock signal output buffer 110 with reference to the output signal of the interrupt decoder 220, and the clock signal output buffer 110. The PLL logic unit 230 outputs the reference clock signal Ref-8K synchronized with the enable signal of the processor 210 to the PLL logic unit 230.

That is, the network synchronization clock signal selection device of the present invention outputs only the reference clock signal Ref-8K synchronized from each digital trunk card 100, and also interrupts it when the line is activated to the main control card 200. In addition, the main control card 200 has an interrupt decoder 220 for decoding it.

According to FIG. 3, the digital trunk card 100 is mounted to output a synchronized clock signal S8K at line activation and is connected to the clock signal output buffer 110 input. In addition, the interrupt generator 120 generates a line card interrupt of the corresponding slot in order to inform the main control card 200 that it is connected to the external network.

The interrupt decoder 220 of the main control card 200 analyzes the interrupt generated from each slot, and the processor 210 enables the external network by enabling the output buffer 110 of the synchronized clock signal S8K of the corresponding slot. And the reference clock signal Ref-8K synchronized with the PLL logic unit 230 are input.

When the system is initialized, the main control card 200 has a database (DB) of what kind of line card is mounted in each slot, so that the buffer of the synchronized clock signal (S8K) is decoded by decoding the interrupt generated from each line card. You can control the output.

As described above, the network synchronous clock signal selection device of the switching system according to the present invention is equipped with an output buffer for the clock signal to inform the main control card of the clock signal as an interrupt and output the buffer enable clock signal. By intermittent operation, it provides the advantage that the clock signal synchronized with the external network can be selected by the simple circuit configuration.

The invention is not limited to the embodiments described herein, but may be modified and changed by those skilled in the art without departing from the spirit and scope described in the appended claims.

Claims (1)

An apparatus for selecting a network synchronization clock signal of a switching system, A digital trunk card having a synchronization signal generator for generating a synchronized clock signal, a clock signal output buffer for interrupting the output of the clock signal, and an interrupt generating means; A main control card having a PLL logic section, a processor section, and an interrupt decoder section; The interrupt generating means informs the interrupt decoder of an interrupt signal of a corresponding line when the line of the switching system is activated, and the interrupt decoder decodes the interrupt signal and outputs the interrupt signal to the processor, wherein the processor decodes the interrupt decoder. A predetermined enable signal is applied to the clock signal output buffer by referring to an output signal, and the clock signal output buffer is configured to output a clock signal synchronized with the enable signal of the processor unit to the PL logic unit. Network synchronous clock signal selection device for switching system.