KR19990020368A - Stand-alone interface device in private switching system - Google Patents

Abstract

end. The technical field to which the invention described in the claims belongs

Stand-alone interface device in private switching system

I. The technical problem that the invention is trying to solve

An interface device for generating independent synchronization signals in a private exchange system is provided.

All. Summary of the Solution of the Invention

A clock generator for dividing a clock supplied from an oscillator to generate and output a reference clock, a frame signal generator for receiving the reference clock to generate and output a frame synchronization signal, and supplying the generated frame synchronization signal and the main device It is composed of a buffer for receiving and receiving the data frame synchronization signal.

la. Important uses of the invention

Accuracy can be improved by generating independent synchronization signals in a private exchange system.

Description

Stand-alone interface device in private switching system

The present invention relates to an independent drive interface device in a private exchange system, and more particularly, to an interface device for generating independent synchronization signals in a private exchange system.

In general, a private switching system is connected to a trunk line trunk such as an analog trunk, a digital trunk, an E1 or T1 ISDN trunk, and receives a clock from the trunk line trunk to generate a synchronization signal.

1 is a diagram illustrating a connection between a main device and a trunk in a conventional private switching system, wherein the main device 100, an ISDN digital trunk 110, and a 2B + D digital trunk 120, 130, and a BSI (base station interface device) 140 and a selection unit 150 are shown in FIG. It is composed.

Referring to FIG. 1, the main device 100 receives a clock from a connected trunk 110 to 140 to generate a synchronization signal, and supplies a frame synchronization signal generated to each trunk 110 to 140. ISDN digital trunks 110 have the highest priority, and 2B + D digital trunks 120,130 have the next highest priority. Since the ISDN digital trunk 110 has the highest priority, the ISDN digital trunk 110 supplies the clock supplied from the trunk line to the main device 100. Meanwhile, the 2B + D digital trunks 120 and 130 supply the reference clock to the main device 100 through the selector 150 when the clock is not supplied from the ISDN digital trunk 110 according to the priority. Since BSI140 is a subscriber card, it has a lower priority than digital trunks 110-130. The selector 150 receives the clocks from the 2B + D digital trunks 120 and 130 and the BSI140, and supplies the clocks supplied from the 2B + D digital trunks 120 and 130 and the BSI140 to the main device 100 according to priority.

In the conventional private switching system, the frame synchronization clock is supplied from several service cards and the highest priority is used as the reference clock. That is, the conventional private switching system receives the reference clock from the service card with the highest priority and uses it as the system clock. Conventional private switching system generates a frame synchronization and a clock synchronized with the clock received from the service card to use as a highway source clock. However, in the case of a system in which priorities for service cards are not defined in the conventional private exchange system, there is a problem in that the service cards cannot be flexibly operated by changing the arrangement of the service cards. For example, if the BSI140 is operated with a 2B + D digital trunk 120,130, the BSI140 will be affected by the system clock operated by the clock source supplied from the 2B + D digital trunk 120,130, or the system's own clock when the BSI140 is active. Will receive. The precision of the clock used in the conventional system is about 30 PPM, which does not satisfy the 5 PPM required by the deck specification, which causes operational problems when the conventional private exchange system is used as a text system. In addition, the conventional private switching system is unsuitable for a deck system requiring a precise frame synchronization signal since the service card changes to an active or inactive state.

Accordingly, an object of the present invention is to provide an independent drive interface device in a private exchange system.

Another object of the present invention is to provide an interface device for generating independent synchronization signals in a private exchange system.

It is another object of the present invention to provide an interface card for a deck of an independent synchronous driving method in a private exchange system.

According to an aspect of the present invention, a clock generator for generating and outputting a reference clock by dividing a clock supplied from an oscillator, a frame signal generator for generating and outputting a frame synchronization signal by receiving the reference clock, And a buffer configured to receive the generated frame synchronization signal and the frame synchronization signal supplied from the host device to transmit and receive data.

1 is a block diagram of an apparatus for supplying a synchronization signal in a conventional private exchange system.

2 is a block diagram of an interface device for generating a synchronization signal in a private exchange system according to an embodiment of the present invention.

FIG. 3 is a block diagram illustrating a synchronization signal generation unit shown in FIG. 2.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. First of all, in adding reference numerals to the components of each drawing, it should be noted that the same components have the same reference numerals as much as possible even though they are shown in different drawings. In addition, in the following description of the present invention, if it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

2 is a block diagram of an interface device for generating a synchronization signal in a private exchange system according to an embodiment of the present invention, and includes a synchronization signal generation unit 300 and a buffer 310.

3 is a block diagram illustrating the synchronization signal generator shown in FIG. 2 and includes an oscillator 301, a quarter divider 302, an inverter 303, a half divider 304, a counter 305, 306, and an AND gate 307.

Referring to Figures 2 and 3 will be described the operation of the interface device for generating an independent synchronization signal in a private exchange system according to an embodiment of the present invention. The quarter divider 302 receives a clock of 16.384 MHz from the oscillator 301 and performs quarter division to output a clock of 4.096 MHz to the inverter 303. The 1/2 divider 304 performs a 1/2 division of the clock supplied from the inverter 303 to generate and output a 2.048 MHz reference clock. Counters 305 and 306 receive the reference clock to generate and output a synchronization signal. The AND gate 307 receives the signals output from the counters 305 and 306 and performs the logic of the logical product to generate and output a frame synchronization signal. The buffer 310 is an elastic buffer and receives a frame synchronization signal from the AND gate 307 and a reference clock from the 1/2 divider 304. In addition, the buffer 310 receives a frame synchronization signal and a clock from the main device 100 and transmits and receives data between the BSI140 and the main device 100. The quarter divider 302 and the half divider 304 receive a reset signal from the main device 100 to generate a reference clock. The reset signal is implemented to generate the frame synchronizing signal of the master device 100 and the frame synchronizing signal generated by the synchronizing signal generator 300 at the same time. Accordingly, the buffer 310 receives a frame synchronization signal as a reference for data input / output of both ends, that is, a frame synchronization signal supplied from the main device 100 and a frame synchronization signal supplied from the synchronization signal generator 300 start at the same time.

As described above, the present invention can generate a clock and generate a frame synchronization signal by the interface card of the base station of the private switching system, so that stable operation can be performed. In addition, the present invention has the advantage that it is possible to transmit the data from each deck base station by generating a stable clock of its own regardless of the clock shake caused by the use of other digital trunks in the private switching system. In addition, the present invention has the advantage of reducing the data slip phenomenon caused by the clock difference between the system and the interface device by controlling the reset operation of the stand-alone interface device in the private exchange system. That is, the present invention provides the data by applying the reset signal so that the independent drive interface device of the private exchange system can generate the frame synchronization signal, which is the reference for data input and output across the buffer, at the same time as the frame synchronization signal supplied from the system. Slip phenomenon can be reduced.

Claims (6)

In a stand-alone interface device in a private exchange system, A clock generator for dividing a clock supplied from the oscillator to generate and output a reference clock; A synchronization signal generation unit receiving the reference clock to generate and output a frame synchronization signal; And a buffer receiving and receiving data from the frame synchronizing signal output from the synchronizing signal generating unit and the frame synchronizing signal supplied from the main device of the system. The method of claim 1, Independent drive system in the private exchange system, characterized in that the buffer is implemented as an elastic buffer. The method of claim 1, And the clock generator is implemented as a divider for dividing a clock supplied from the oscillator to generate a reference clock. The method of claim 1, The sync signal generator is implemented with first and second counters and an end gate, The first counter receives a reference clock from the clock generator to perform a counting operation, and outputs a resultant first signal to the second counter. The second counter receives the first signal output from the first counter, receives a reference clock from the clock generator, performs a counting operation, and outputs a resultant second signal. And the AND gate receives the first signal and the second signal and performs a logical operation of a logical product to generate and output a frame synchronizing signal. The method of claim 3, And the frequency divider generates a reference clock by receiving a reset signal from a main device of the system. In a stand-alone interface device in a private exchange system, A synchronization signal generator for receiving a clock from an oscillator, dividing the clock to generate a reference clock, and generating and outputting a frame synchronization signal from the reference clock; And a buffer configured to receive a frame sync signal from the sync signal generator, and a buffer to transmit data transmitted and received by a frame sync signal from a system.