KR20000007200A - Device for receiving clock from digital clock supplying device of radio subscriber network system - Google Patents

Abstract

PURPOSE: A device for receiving a clock from a digital clock supplying device of a radio subscriber network system is provided to enable a network synchronization even in case of using the existed telephone network. CONSTITUTION: A device for receiving a clock contains; a standard clock receiving unit(20) of a higher station for receiving a standard clock from a switching station or a base station controller; a clock selecting unit(30) selecting one from the outputs from a Digital Office Timing Supplier(DOTS) clock receiving unit and the standard clock receiving unit of the higher station for selecting the most satisfactory port from plural ports of the selected clock as a standard clock for a synchronizing; and a system clock generating unit(40) for being connected to the output terminal of the clock selecting unit for synchronizing an oscillator output clock to the standard clock selected from the outside by using a Digital Processing-Phase Locked Loop(DP-PLL).

Description

Clock Receiving Device from Digital Clock Supply of Wireless Subscriber Network System

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wireless subscriber network system, and more particularly, to a clock receiving apparatus from a digital clock supply device of a wireless subscriber network system that enables a network synchronizer even when using an existing telephone network.

In general, in case of DCS or PCS system, each system independently receives its clock from GPS (Global Positioning System) to synchronize the system, but in the case of WLL system, it is clocked from higher station (e.g. switch or base station controller). It takes predominant synchronous method of receiving.

In other words, the system clock is synchronized by receiving a notice reference input clock from a higher station, and when the external input reference clock changes, the system clock also changes.

Figure 1 is a block diagram of a conventional WLL system network board, the upper station reference clock receiving unit for receiving a 2.048MHz 2 port and 8KHz 2 port of RS-422 level from the switch or base station controller to convert to the TTL level required for board operation (1 And a clock selector (2) for selecting a clock having the best state among the 2.048 MHz two ports and the 8 KHz two ports received from the upper station reference clock receiver (1) to provide a system clock for synchronization, and the clock selection. A system clock generator (3) connected to an output terminal of the unit (2) for synchronizing an oscillator output clock to an externally selected synchronization reference clock using a DP-PLL (Digital Processing-Phase Locked Loop); A clock divider (4) connected to the unit (3) for dividing a system clock synchronized with an external reference clock into respective clocks of each board of the system, and a clock divided by the clock divider (4).Is composed of a clock distributor (5) for distributing to each board takes over the driver.

In the conventional WLL system configured as described above, when 2.048MHz 2 port and 8KHz 2 port of RS-422 level are received from the exchange or base station controller to the host station reference clock receiver 1, it is converted into the TTL level required for board operation and the clock is selected. Through the section 2, a clock having a good state is selected and provided as a synchronous system clock.

In addition, the oscillator output clock is synchronized to an externally selected synchronization reference clock through the system clock generator 3, and a system clock synchronized to an external reference clock is clocked through the clock divider 4 to each board of the system. After each clock was divided, it was distributed to each required board through the clock distributor 5.

In the conventional WLL system, however, the base station controller receives the clock from the switch and the base station receives the clock from the base station controller to synchronize the clock. However, the clock selector 2 can select only one good clock port among the clock signals of the various ports. For example, when a two-wire analog line is used without using the E1 line from the upper station, there is a drawback that the clock cannot be received from the upper station.

The present invention is to solve the above-mentioned shortcomings, by receiving a reference clock directly from the DOTS (Digital Office Timing Supplier) to enable network synchronization even when using the existing telephone network using a two-wire analog line system The present invention provides a clock receiving device from a digital clock supply device of a wireless subscriber network system that can reduce a clock variation.

Another object of the present invention is that when receiving the reference clock from the upper station, the accuracy decreases every time the first level is lowered, thereby improving the accuracy of the clock by receiving the highest clock from the DOTS, and having a strength in jitter and wonder. To provide a clock receiving device from a digital clock supply of a wireless subscriber network system that can improve the performance of.

1 is a block diagram of a conventional WLL system network synchronizer board

Figure 2 is a block diagram of the present invention DOTS receiving network board

3 is a block diagram showing a detailed configuration of a DOTS clock receiver of FIG.

<Explanation of symbols for main parts of drawing>

5: RS-422 Receiver 6: Transformer

7: Clock extraction circuit 8: Clock selection circuit

10: DOTS clock receiver 20: Host reference clock receiver

30: clock selector 40: system clock generator

50: clock divider 60: clock divider

The present invention for achieving the above object is characterized in that it further comprises a DOTS clock receiver in front of the existing clock selector.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of the present invention, in which a pure clock is directly received from a DOTS and a DOTS clock receiver 10 for receiving an E1 signal and extracting a clock therefrom, and a higher station receiving a reference clock from an exchange or base station controller. By selecting one of the reference clock receiving unit 20, the output of the DOTS clock receiving unit 10 and the upper station reference clock receiving unit 20 to select the best one of several ports of the selected clock as the synchronization reference clock A system clock generator 40 connected to a clock selector 30, an output terminal of the clock selector 30 to synchronize an oscillator output clock with an externally selected synchronization reference clock using DP-PLL, and A clock divider 50 connected to a system clock generator 40 to divide a system clock synchronized with an external reference clock to respective clocks of each board of the system, and the clock divider 50. Is composed of a clock frequency divider by a clock distributor 60 for distributing to each board takes over the driver.

3 is a detailed configuration of the DOTS clock receiver 10, an RS-422 receiver 5 receiving a pure clock from a DOTS device, a transformer 6 for receiving an E1 signal from a DOTS device and converting it to a TTL level; A clock extraction circuit 7 for extracting a clock from the transformer 6 and a clock selection circuit for selecting any one of a clock of the RS-422 receiver 5 and a clock of the clock extraction circuit 7; 8).

Referring to the operation of the present invention configured as described above is as follows.

First, when the reference clock is input to the upper station reference clock receiver 20 from an exchange or a base station controller, the upper station reference clock receiver 20 receives a 2.048 MHz 2 port and an 8 KHz 2 port of RS-422 level to operate the board. Convert to the TTL level required for.

In addition, when the pure clock is input to the DOTS clock receiving unit 10 through DOTS, the clock selector 30 to the pure clock received by the DOTS clock receiving unit 10 and the reference clock receiving unit 20 of the higher station. After selecting one of the received reference clocks, one of the selected ports of the selected clock is selected as the reference clock for synchronization.

When the clock is selected by the clock selector 30 in this manner, the system clock generator 40 synchronizes the oscillator output clock to the synchronization reference clock selected by the clock selector 30 by using the DP-PLL.

In addition, the clock divider 50 divides the system clock synchronized with the external reference clock into respective clocks required for each board of the system, and sends the divided clock to the clock divider 60. The clock divider 60 divides the divided clock into the clock divider 60. It is distributed to each board through the driver.

In the DOTS clock receiver 10, the E1 signal and the pure clock come out together in the case of the new type, but the pure clock does not come out separately in the case of the old type, so only the E1 signal comes out. It can be received through the transformer 6 and the clock extraction circuit 7, and in the case of new equipment, it can be received through the RS-422 receiver 5.

Any one of the clock of the RS-422 receiver 5 and the clock of the clock extracting circuit 7 received in this way is selected by the clock selecting circuit 8 and sent to the clock selecting unit 30 in FIG. will be.

Therefore, in the present invention, even when a two-wire analog line is used from the upper station, the clock can be received through the DOTS clock receiver 10 as described above, and thus, even when an existing telephone network is used, the synchronizer is possible.

In addition, in the present invention, since the highest clock is directly received from the DOTS 10, when the reference clock is received from the upper station, the accuracy of the clock is improved even when the first level is lowered, even when the first clock is lowered.

As described above, the present invention could not receive the clock from the upper station when a two-wire analog line was used from the upper station. However, the reference clock from the upper station is further provided by simply providing a DOTS clock receiving unit 10. When receiving through the station reference clock receiving unit 20 and using a 2-wire analog line, the DOTS clock receiving unit 10 allows the clock to be received, thereby having the effect of enabling the network.

In particular, the highest clock is directly received from the DOTS clock receiver 20 to improve the accuracy of the clock as well as to improve the performance of the system by improving jitter and wonder.

Claims (2)

In the wireless subscriber network system that receives the clock from the host station, selects the clock, distributes and distributes the clock to each required board, A DOTS clock receiver for selecting and extracting a clock when receiving a pure clock directly from DOTS and receiving an E1 signal; An upper station reference clock receiver which receives a reference clock from an exchange or base station controller; A clock selector for selecting one of the outputs of the DOTS clock receiver and the upper station reference clock receiver to select one of the selected ports of the selected clock as the synchronization reference clock; A system clock generator connected to an output terminal of the clock selector to synchronize an oscillator output clock with an externally selected synchronization reference clock using DP-PLL; A clock divider connected to the system clock generator to divide a system clock synchronized with an external reference clock into respective clocks required by each board of the system; And a clock divider for distributing the clock divided by the clock divider to each required board through a driver. The method of claim 1, wherein the DOTS clock receiver, RS-422 receiver receiving pure clock from DOTS equipment, Transformer that receives E1 signal from DOTS device and converts it into TTL level, A clock extraction circuit for extracting a clock from the transformer; And a clock selection circuit for selecting any one of a clock of the RS-422 receiver and a clock of a clock extracting circuit.