KR19990058828A - Network synchronizer - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a network synchronization device, and more particularly, to a network synchronization device connected to an exchange system for realizing network synchronization and providing various system clocks.

The present invention provides an apparatus for selecting a normal first reference clock (PRC) from a plurality of reference clocks; An apparatus for selecting a normal second reference clock (SRC) from a plurality of reference clocks; And a phase locked loop receiving first and second reference clocks from the multiplexers 1 and 2 and outputting a system clock.

The present invention configured as described above can achieve more stable network synchronization by using the normal first and second reference clocks detected from a plurality of reference clocks, and minimize the phase change of the system clock even when there is a state change of the reference clock source. In addition, various types of network-synchronized clocks are provided by a phase-locked loop body to provide various types of network-synchronized system clocks with a small volume of network synchronization circuits.

Description

Network synchronizer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a network synchronizer, and more particularly, to a network synchronizer connected to a local exchange (LE) to realize network synchronization and to provide various system clocks in a system requiring a network synchronization function. .

The most inexpensive and time-consuming part of constructing a mobile communication network designed based on conventional cables is the routing work for connecting each subscriber to a local exchange. In most cases, for a connection between a public switched telephone network (PSTN) and a subscriber where no subscriber line is available, it is easier to replace the fixed subscriber line with a wireless connection that can be established quickly and easily. to be.

The subscriber network thus comprises a base station connected to the exchange and a subscriber terminal (mobile phone) wirelessly connected with the base station in the same manner as in a normal mobile telephone network. Such a system is called a wireless subscriber network (WIRELESS LOCAL LOOP: WLL). The wireless subscriber network has been proposed for basic application purposes such as expansion and replacement of circuits in densely populated and widely distributed areas such as farming and fishing villages, urban population centers, and emergency communication in the event of a disaster.

This technology can be installed regardless of distance and terrain, and economical, and it is emerging as a system capable of voice and high-speed data transmission or multimedia service.

The wireless subscriber network can be applied to all kinds of wireless systems using the wireless subscriber network to replace the subscriber line between the fixed network and the subscriber. The wireless subscriber network system includes a Local Exchange (LE), a Radio Distribution Unit (RDU), also referred to as a wireless distribution or switching center, a number of base stations (Racs), called a radio transmission station, and a fixed station. It includes a number of fixed subscriber unit (FSU) and telephone subscribers, also called subscriber end or subscriber premises equipment.

Synchronizing a network is a very important task in a mobile communication system including a plurality of transmitting and receiving devices connected to a network, such as the wireless subscriber network configured as described above.

In the prior art, elements such as a counter, a phase comparator, and a low pass filter (LPF) have been used to configure such a network synchronizer. In order to implement individual functions of the devices and to control the phase change, a plurality of phase detectors were used, and a memory for collecting statistical data was included. 1 is a block diagram of a network synchronization device according to the prior art. Hereinafter, a configuration of a network synchronizer according to the prior art will be described with reference to FIG. 1.

First, three reference clocks are input from a trunk, and one of them is input to a digital phase locked loop (PLL). In order to detect slip and detect phase error, a separate slip counter and phase detector are implemented externally. The sleep counter and phase detector are designed to control both the operation of the phase locked loop in software.

However, since the network synchronization device according to the related art configured as described above has controlled the operation of the phase-locked loop at the software level, the hardware circuit and software structure for implementing the network synchronization function are complicated and difficult to implement. In addition, there was a problem that the size of the software function block occupied by the system is very large.

Therefore, in order to solve the above problems, the present invention uses two reference clocks simultaneously and one of them is used as a primary reference clock (PRC) for network synchronization. By using it as a Secondary Reference Clock (SRC) to be immediately replaced when there is an error in the first reference clock, network synchronization is smoothly performed while minimizing the need for separate hardware and software even when the reference clock is changed. It is an object of the present invention to provide a network synchronization device configured to be carried.

1 is a structural diagram of a network synchronizer according to the prior art;

2 is a block diagram of a network synchronization device according to the present invention;

3 is a schematic configuration diagram of a network synchronization device according to the present invention;

<Description of the symbols for the main parts of the drawings>

110,140: reference clock receive buffer

120,150: reference clock phase error detection engine

130,160: reference clock input table

170: phase locked loop (PLL)

180: system clock divider

190: system clock generator

One preferred embodiment of the present invention devised to achieve the object as described above,

An apparatus for selecting a normal first reference clock (PRC) from a plurality of reference clocks;

An apparatus for selecting a normal second reference clock (SRC) from a plurality of reference clocks; And

And a phase locked loop for receiving first and second reference clocks from the multiplexers 1 and 2 and outputting a system clock.

In one embodiment of the present invention, the plurality of reference clocks are preferably extracted from the data transmitted through the relay line,

The apparatus for selecting the first reference clock includes: a reference clock receiving buffer configured to receive a reference clock;

A reference clock error detector for receiving a reference clock stored in the reference clock receiving buffer in order and checking whether the reference clock is normal; And

Preferably, the reference clock includes a reference clock input table configured to receive and register a reference clock normally determined by the reference clock error detector from the reference clock receiving buffer.

Preferably, the reference clock error detector checks whether the reference clock is normal by checking phase information of the received reference clock.

When the reference clock error detector receives an abnormal reference clock, the reference clock error detector may continuously check the next reference clock without registering in the reference clock input table.

The apparatus for selecting the second reference clock may include: a reference clock receiving buffer configured to receive a reference clock;

A reference clock error detector for receiving a reference clock stored in the reference clock receiving buffer in order and checking whether the reference clock is normal; And

Preferably, the reference clock error detector includes a reference clock input table that receives and registers a reference clock normally determined from the reference clock receiving buffer.

Preferably, the reference clock error detector checks whether the reference clock is normal by checking phase information of the received reference clock.

When the reference clock error detector receives an abnormal reference clock, the reference clock error detector may continuously check the next reference clock without registering in the reference clock input table.

Preferably, the output clock of the phase locked loop is converted into various types of clocks required by the system by passing through a clock divider.

Preferably, the network synchronization device is immediately replaced with a second reference clock when there is an error in the first reference clock.

Preferably, the network synchronous device generates and provides a reference clock using a separate system clock generator when a plurality of input reference clocks are all abnormal or none is input.

The system clock generator preferably uses a high-definition clock as a source,

Preferably, the network synchronizer minimizes a phase change of a system clock when a state of the plurality of reference clock sources is changed.

2 shows a configuration diagram of a network synchronization device according to the present invention. As shown, the reference clock receiving buffer 110, 140 for receiving a reference clock; A reference clock phase error detection engine (120) (150) coupled with the reference clock receive buffer; A reference clock input table (130) (160) connected to the reference clock phase error detection engine and a reference clock receive buffer; A phase locked loop (170) connected to the reference clock input table; A system clock divider (180) associated with the phase locked loop; And a system clock generator 190 for receiving a reference clock.

The reference clock reception buffer 110 is responsible for receiving a reference clock extracted from an external trunk interface module. The reference clock phase error detection engine 120 checks phase information of the reference clock received from the reference clock reception buffer 110 to determine whether the reference clock is normally received. When the reference clock is normal, the reference clock is registered in the reference clock input table 130 to be used as the first reference clock PRC. If the reference clock is abnormal, it is not registered in the reference clock input table 130 and continues to check whether it is normal.

The reference clock phase error detection engine 150 and the reference clock input table 160 also perform the same functions as 120 and 130. Only the reference clock phase error detection engine 150 and the reference clock input table 160 provide the selected reference clock as the second reference clock SRC. That is, one of the clocks other than the reference clock selected as the first reference clock PRC may be used as the second reference clock SRC.

As described above, the network synchronization device according to the present invention has two detection engines 120 and 150 for selecting the first reference clock PRC and the second reference clock SRC. The two detection engines 120 and 150 check the reference clock from the reference clock receive buffers 110 and 140 and reflect the result to the reference clock input tables 130 and 160 so that the phase locked loop 170 can be used. In this case, the first reference clock PRC and the second reference clock SRC can be simultaneously received and used.

The phase locked loop 170 simultaneously receives two reference clocks PRC and SRC. The system clock divider 180 is obtained by dividing the output of the phase locked loop 170 to make various types of clocks required by the system.

The system clock generator 190 generates and provides a reference clock in the system itself when none or all of the reference clocks are extracted from the relay line. Therefore, the system clock generator 190 uses a high-definition clock as a source.

The reference clock reception buffer 110, 140, the reference clock phase error detection engine 120, 150, and the reference clock input table 130, 160 receive a normal reference clock from a plurality of received reference clocks. Perform the multiplexing operation of selecting. 3 shows a schematic configuration diagram of a network synchronization device according to the present invention. As shown, multiplexer 1 and multiplexer 2 select one normal reference clock from a plurality of reference clocks and provide it to the phase locked loop. The detection engine controls the selection terminal such that the multiplexer selects one normal reference clock.

The present invention operating as described above has a very simple control structure, which can provide the required clock accuracy at the sub-exchange level and is easily applicable. In addition, various types of network-synchronized clocks are provided by the phase-lock loop itself, so a small volume of network synchronization circuits can provide various types of network-synchronized system clocks. As a result, the phase shift of the system clock is minimized when there is a state change of the reference clock source.

Claims (13)

An apparatus for selecting a normal first reference clock (PRC) from a plurality of reference clocks; An apparatus for selecting a normal second reference clock (SRC) from a plurality of reference clocks; And And a phase locked loop for receiving a first and second reference clocks from the multiplexers 1 and 2 and outputting a system clock. The network synchronization device of claim 1, wherein the plurality of reference clocks are extracted from data delivered through a relay line. The apparatus of claim 1, wherein the apparatus for selecting the first reference clock comprises: A reference clock receiving buffer for receiving a reference clock; A reference clock error detector for receiving a reference clock stored in the reference clock receiving buffer in order and checking whether the reference clock is normal; And And a reference clock input table for receiving and registering a reference clock normally determined by the reference clock reference clock error detector from the reference clock receiving buffer. The network synchronizer of claim 3, wherein the reference clock error detector checks whether a reference clock is normal by checking phase information of a received reference clock. 4. The network synchronizer of claim 3, wherein the reference clock error detector continuously checks a next reference clock without registering in the reference clock input table when the received reference clock is abnormal. The apparatus of claim 1, wherein the device for selecting the second reference clock comprises: A reference clock receiving buffer for receiving a reference clock; A reference clock error detector for receiving a reference clock stored in the reference clock receiving buffer in order and checking whether the reference clock is normal; And And a reference clock input table for receiving and registering a reference clock normally determined by a reference clock error detector from the reference clock receiving buffer. The network synchronization device of claim 6, wherein the reference clock error detector checks whether a reference clock is normal by checking phase information of a received reference clock. 7. The network synchronizer of claim 6, wherein the reference clock error detector continuously checks the next reference clock without registering in the reference clock input table when the received reference clock is abnormal. The network synchronizer of claim 1, wherein the output clock of the phase locked loop is converted into various kinds of clocks required by the system by passing through a clock divider. The network synchronization device according to claim 1, wherein the network synchronization device immediately replaces and uses a second reference clock when there is an error in the first reference clock. The network synchronization device of claim 1, wherein the network synchronization device generates and provides a reference clock using a separate system clock generator when all of a plurality of input clocks are abnormal or none is input. 12. The network synchronizer of claim 11, wherein the system clock generator uses a high-definition clock as a source. The network synchronizer of claim 1, wherein the network synchronizer minimizes a phase change of a system clock when a state of the plurality of reference clock sources is changed.