KR100290660B1 - Device for selecting synchronous source clock in dslam and its control method - Google Patents

Abstract

The present invention relates to a synchronization clock selector of an asymmetric digital subscriber network access system for selecting one of a plurality of clocks inputted from the outside in the asymmetric digital subscriber network access system and input to the reference signal input terminal of the PLL circuit and its operation method. According to the present invention, the synchronization clock selector of the asymmetric digital subscriber network access system according to the present invention and its operation method converts the E1, STM-1 clock and the local oscillation clock into a constant frequency clock through three dividers: The controller detects the E1 and STM-1 clock states in the state of inputting to the input terminal of 1 mux, and when both signals are in a normal state, the mux is controlled to select and output the divided E1 clocks, and the STM-1 clock. If the normal state is selected, the divided STM-1 clock is selected and outputted. If both clocks are abnormal, the divided local oscillation clock is selected. This allows the asymmetric digital subscriber network access system to match the PSTN switching network and the ATM switching network using a single PLL circuit, and outputs the status information on the clock selected by the mux to the PLL circuit. There is an excellent effect to recognize the signal input to the.

Description

DEVICE FOR SELECTING SYNCHRONOUS SOURCE CLOCK IN DSLAM AND ITS CONTROL METHOD}

The present invention relates to a synchronization clock selector of an asymmetric digital subscriber network access system for selecting one of a plurality of clocks inputted from the outside in the asymmetric digital subscriber network access system and input to the reference signal input terminal of the PLL circuit and its operation method. will be.

In general, asymmetric digital subscriber network access system (DIGITAL SUBSCRIBER LINE ACCESS MULTIPLEXER) is used by many ADSL (ASYMMETRIC DIGITAL SUBSCRIBER LINE) modem subscribers to use high-speed data service such as high-speed internet service, LAN, VOD, etc. by using existing telephone line. A system that matches the ATM switching network or the PSTN switching network.

In order for the asymmetric digital access network access system to match the ATM switching network or the PSTN switching network, it is necessary to maintain synchronization with the ATM switching network and the PSTN switching network, and a circuit therefor is referred to as a PLL (PHASE LOCKED LOOP; hereinafter referred to as PLL). Circuit.

On the other hand, since the signals used in the switching network use different frequencies, and the PLL circuit adjusts phase synchronization using only one reference signal, the asymmetric digital subscriber network access system uses PLL circuits corresponding to the number of frequencies inputted from the matching switching network. A scheme was used to match only one switching network, either using a single PLL circuit.

However, when PLL circuits are used as many as the number of input frequencies, there is a problem in that the circuit configuration becomes complicated. In the case of using one PLL circuit, there is a problem in that the data service width is reduced because only matching with a single switching network is possible.

Accordingly, the present invention has been made to solve the above problems, and an object of the present invention is to allow an asymmetric digital subscriber network access system to match a PSTN switching network and an ATM switching network using a single PLL circuit. The present invention provides a synchronization clock selection device of a connection system and a method of operating the same.

In order to achieve the above object, the synchronization clock selector of the asymmetric digital subscriber network access system according to the present invention includes a first divider which receives an E1 clock, divides it into a 64 kHz clock, and STM-1 in an ATM switching network. A second divider which receives the clock and divides it into a 64 kHz clock, a third divider which receives the divided oscillation clock and converts it into a 64 kHz clock, and outputs the first, second, and second dividers. 3: 1 mux for selecting one of the clocks and outputting them to the reference signal input terminal of the PLL unit, and monitoring the states of the E1 clock and the STM-1 clock after receiving the E1 monitoring signal and the STM-1 monitoring signal. Controlling the controller to select a normal clock according to priority, and receiving the signal input state signal from the controller, processing the signal, and outputting the signal to the display device. It characterized by comprising signal detecting portion to be recognized.

In order to achieve the above object, a method of operating a synchronization clock selection device of an asymmetric digital subscriber network access system according to the present invention includes a first step of receiving an E1 monitoring signal and an STM-1 monitoring signal, and determining whether the E1 clock is normal. In case of normal operation, the second step of controlling the E1 clock divided by 3: 1 mux and outputting it to the reference signal input terminal of the PLL unit, and if the E1 clock is abnormal in the second step, determines whether the STM-1 clock is normal. If normal, the STM-1 clock divided by 3: 1 mux is selected and controlled to be output to the reference signal input terminal of the PLL unit, and then the third step proceeds to the second step, and the STM-1 clock is abnormal in the third step. If the 3: 1 mux is divided into a local clock is selected to control to output to the reference signal input terminal of the PLL unit, characterized in that the fourth step proceeds to the second step.

1 is a schematic block diagram of a general DSLAM system;

2 is a block diagram illustrating a PLL block to which a synchronous one-clock selection device of an asymmetric digital subscriber network access system according to an embodiment of the present invention is applied;

3 is a detailed block diagram of a synchronization clock selector of an asymmetric digital subscriber network access system according to an embodiment of the present invention;

4 is a flowchart illustrating an operation method for a synchronous clock select apparatus of an asymmetric digital subscriber network access system according to an embodiment of the present invention.

<Explanation of symbols for main parts of the drawings>

100: first divider 110: second divider

120: third divider 130: buffer

200: 3: 1 mux 300: control unit

400: signal detection unit 410: redundancy drive unit

Hereinafter, a synchronization clock selection device and an operation method of an asymmetric digital subscriber network access system according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a schematic block diagram of a general DSLAM system. The upper self-uplink board 1 is optically interfaced with an ATM switching network and simultaneously interfaced to a PSTN switching network to process a received signal. And a modem self optical interface board.

In addition, the upper self-uplink board 1 should select a constant frequency clock as a synchronization source to interface with the ATM switching network or the PSTN switching network, and the PLL block shown in FIG.

The synchronization source selector 1000 receives an STM-1 clock (approximately 155.52 kHz) from an ATM switching network, receives an E1 clock from a PSTN switching network, and divides each of them by receiving a local oscillation clock generated by itself. It converts the clock and selects one of the divided clocks and transmits them.

The PLL unit 2000 receives the divided clock selected by the synchronization source selector 1000 through a reference signal input terminal, oscillates a frequency that matches the frequency and phase of the divided clock, and outputs an arbitrary device through the output buffer 3000. It plays a role as output.

3 is a detailed block diagram of a synchronous source clock selection device of an asymmetric digital subscriber network access system according to an embodiment of the present invention, and a synchronous source clock selection device of an asymmetric digital subscriber network access system according to an embodiment of the present invention; As shown in FIG. 3, the first, second, and third dividers 100, 110, and 120, the 3: 1 mux 200, the buffer 130, the controller 300, the signal detector 400, and the redundant driver 410.

The first divider 100 receives the E1 clock from the PSTN switching network and divides it into a 64 kHz clock. The second divider 110 receives the STM-1 clock from the ATM switching network and divides it. The third divider 120 receives the local oscillation clock oscillated by the apparatus itself and divides the clock into a 64 kHz clock.

The 3: 1 mux 200 selects one of the clocks output from the first, second, and third dividers 100, 110, and 120 and outputs the selected signal to the reference signal input terminal of the PLL unit 2000.

The buffer 130 receives the E1 monitoring signal and the STM-1 monitoring signal from the PSTN switching network and the ATM switching network, respectively, and receives the status monitoring signal of the upper self-uplink board from the upper self-uplink board itself. Output to.

The controller 300 receives the E1 monitoring signal and the STM-1 monitoring signal, monitors the states of the E1 clock and the STM-1 clock, and then controls the 3: 1 mux 200 to select a normal clock according to priority. Do it.

The signal detector 400 controls the 3: 1 mux 200 by the controller 300 so that the selected clock inputs a signal input state signal including state information in which the selected clock is input through the reference signal input terminal of the PLL unit 2000. The controller 300 receives a signal received from the controller 300 and outputs the signal to the display device to allow an operator to recognize a selection state of the synchronization source clock.

Meanwhile, the controller 300 additionally receives the upper self-uplink board state monitoring signal from the buffer 130 and monitors the state of the redundant board and outputs a control signal corresponding thereto. The redundancy driver 410 receives the control signal from the control unit 300 and processes the signal to output a circuit to control the redundancy state of the upper self-uplink board.

A method of operating a synchronous one-clock selection device of an asymmetric digital subscriber network access system according to an embodiment of the present invention having the above configuration will be described with reference to the drawings.

FIG. 4 is an operational flowchart illustrating a method of operating a synchronous clock select apparatus of an asymmetric digital subscriber network access system according to an embodiment of the present invention, where S represents a step.

Before describing the operation method, the E1 clock, the STM-1 clock and the local oscillation clock are input and divided into the first, second, and third dividers 100, 110, and 120, respectively, and are converted into 64 kHz clocks, which are 3: 1. It is assumed that all of the mux 200 is input, and the content of selecting the clock by controlling the 3: 1 mux 200 by the control unit 300 will be described.

First, the control unit 300 receives the E1 monitoring signal and the STM-1 monitoring signal through the buffer 130 (S1), and determines whether the E1 clock is normal (S2).

If the E1 clock is normal at step S2 (YES), the control unit 300 controls the 3: 1 mux 200 to select the divided E1 clock to divide the reference signal input terminal of the PLL unit 2000. The clock E1 is output (S3) and the process proceeds to step S2.

If the E1 clock is abnormal in step S2 (NO), the controller 300 determines whether the STM-1 clock is normal (S4), and if the STM-1 clock is normal (YES), the controller 300 By controlling the 3: 1 mux 200 to select the divided STM-1 clock, the divided STM-1 clock is output to the reference signal input terminal of the PLL unit 2000 (S5), and the process proceeds to the step S2. do.

If the STM-1 clock is abnormal in step S4 (NO), the control unit 300 controls the 3: 1 mux 200 to select the divided local clock so as to be a reference signal input terminal of the PLL unit 2000. The divided local clock is output (S6), and the process proceeds to the step S2.

Meanwhile, in the above embodiment, the synchronization source clock is automatically selected according to the E1 monitoring signal and the STM-1 monitoring signal, but the operator controls the operator control signal as an arbitrary input means through the buffer 130. ), The 3: 1 mux 200 can be manually controlled by the operator.

As described above, according to the synchronization clock selector and the operating method of the asymmetric digital subscriber network access system according to the present invention, the E1, STM-1 clock and the local oscillation clock are converted into a constant frequency clock through three dividers. The controller detects the E1 and STM-1 clock states in the state of inputting at the input terminal of the 3: 1 mux, and when both signals are in a normal state, the mux is controlled to select and output the divided E1 clocks, and the STM- If only one clock is in a steady state, the divided STM-1 clock is selected and output. If both clocks are abnormal, the asymmetric digital subscriber network access system uses one PLL circuit. By matching the PSTN switching network and ATM switching network, the signal detection unit outputs status information to the clock selected by the mux as an operator. There are excellent effects that to recognize a signal input to the PLL circuit.

In addition, since the operator inputs an operator control signal to the control unit to control the clock selection operation of the mux, there is an excellent effect that the clock can be manually selected.

Claims (5)

The E1 clock, the STM-1 clock, the local oscillation clock, the E1 monitoring signal, and the STM-1 monitoring signal are inputted in the upper self uplink board of the asymmetric digital subscriber network access system. In the device for selecting the clock as the synchronization source clock and output to the reference signal input terminal of the PLL unit, A first divider which receives an E1 clock and divides it into a 64 kHz clock; A second divider which receives the STM-1 clock from the ATM switching network and divides it into 64 kHz clock; A third divider which receives the local oscillation clock and divides it into 64 kHz clock, 3: 1 mux for selecting one of the clocks output from the first, second, and third dividers and outputting them to the reference signal input terminal of the PLL unit; A control unit which receives the E1 monitoring signal and the STM-1 monitoring signal, monitors the states of the E1 clock and the STM-1 clock, and then controls the 3: 1 mux to select a normal clock according to priority; The synchronization clock of the asymmetric digital subscriber network access system, characterized in that the control unit receives a signal input state signal, and processes the signal and outputs it to the display device so that the operator can recognize the selection state of the synchronization clock. Selector. The method of claim 1, Synchronization of the asymmetric digital subscriber network access system characterized in that the front end of the control unit is further provided with a buffer for receiving the E1 monitoring signal, STM-1 monitoring signal and the upper self-uplink board status monitoring signal and output to the control unit. One clock selector. The method according to claim 1 or 2, The control unit receives an upper self-uplink board state monitoring signal from the buffer and monitors the state of the redundant board and outputs a control signal corresponding thereto. Synchronization of an asymmetric digital subscriber network access system, characterized in that the control unit receives the control signal and the signal processing to output the circuit to the circuit for controlling the redundancy state of the upper self-uplink board One clock selector. The method according to claim 1 or 2, And said 3: 1 mux inputs an operator control signal to a controller through a buffer and selects one of the manually controlled and divided input clocks. The three clocks are divided by receiving E1 clock, STM-1 clock, local oscillation clock, E1 monitoring signal, and STM-1 monitoring signal in upper self uplink board of asymmetric digital subscriber network access system. In the operating method of the device for selecting the clock as a synchronization source clock and outputting it to the reference signal input terminal of the PLL unit, A first step of receiving an E1 monitoring signal and an STM-1 monitoring signal; Determining whether the E1 clock is normal, and if it is normal, selecting a E1 clock divided by a 3: 1 mux and controlling the E1 clock to be output to a reference signal input terminal of the PLL unit; In the second step, if the E1 clock is abnormal, it is determined whether the STM-1 clock is normal. If the E1 clock is normal, the STM-1 clock divided by 3: 1 mux is selected and controlled to be output to the reference signal input terminal of the PLL unit. The third step proceeds to a step, In the third step, if the STM-1 clock is abnormal, the fourth step proceeds to the second step after controlling the local clock to which the 3: 1 mux is divided and outputting it to the reference signal input terminal of the PLL unit. A method for operating a synchronization clock selector in an asymmetric digital subscriber network access system.