KR970076175A - Internal clock division of GPIO board - Google Patents
Internal clock division of GPIO board Download PDFInfo
- Publication number
- KR970076175A KR970076175A KR1019960017331A KR19960017331A KR970076175A KR 970076175 A KR970076175 A KR 970076175A KR 1019960017331 A KR1019960017331 A KR 1019960017331A KR 19960017331 A KR19960017331 A KR 19960017331A KR 970076175 A KR970076175 A KR 970076175A
- Authority
- KR
- South Korea
- Prior art keywords
- internal clock
- board
- gpi0
- divider
- register
- Prior art date
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Information Transfer Systems (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
본 발명은 GPI0보드의 컨트롤레지스터에 의해 포트가 인에이블 지정되고 내부클럭의 생성이 지정되는 경우에, 그 인에이블 지정된 포트에 공급되는 내부클럭의 분주수를 결정하기 위한 GPI0보드의 내부클럭 분주제어방법을 제공한다.In the present invention, when the port is enabled by the control register of the GPI0 board and the generation of the internal clock is specified, the internal clock divider of the GPI0 board for determining the frequency division number of the internal clock supplied to the enable- ≪ / RTI >
그에 따라 본 발명은 메인프로세서(2)와 PCI로컬버스(6)와의 데이터인터페이스동작을 위한 복수의 입력포트와 복수의 출력포트를 갖춘 GPI0보드(4)에 있어서; 상기 GPI0보드(4)에서 입력포트와 출력포트에 대해 인에이블 지정되고, 그 인에이블 지정된 포트에 내부클럭의 발생이 지정되면, 디바이더레지스터(22)의 데이터레지스터 내용에 의해 PCI로컬버스(6)의 시스템 클럭에 대한 디바이더에 의해 내부클럭의 분주수(DRx)를 결정하도록 하는 단계로 이루어진 것을 특징으로 한다.Accordingly, the present invention provides a GPI0 board (4) having a plurality of input ports and a plurality of output ports for data interface operation between the main processor (2) and the PCI local bus (6); When the generation of the internal clock is designated to the enabled and designated ports in the GPI0 board 4, the PCI local bus 6 is controlled by the data register contents of the divider register 22, And determining a division number (DRx) of the internal clock by a divider with respect to a system clock of the internal clock.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.
제1도는 본 발명의 방법이 적용된 GPI0보드와 메인프로세서와의 데이터 입/출력구조를 나타낸 도면.FIG. 1 is a diagram illustrating a data input / output structure of a GPIO board and a main processor to which a method of the present invention is applied; FIG.
제2도 (A)는 제1도에 도시된 인터럽트인식레지스터의 인터럽트가 발생된 포트의 확인을 위한 데이터레지스터 내용을 나타낸 도면.FIG. 2 (A) shows contents of a data register for confirming an interrupt-generated port of the interrupt recognition register shown in FIG. 1;
제2도 (B)는 제1도에 도시된 컨트롤레지스터에서 GPI0보드의 동작을 제어하기 위한 데이터레지스터 상태를 나타낸 도면.FIG. 2B shows a data register state for controlling the operation of the GPI0 board in the control register shown in FIG. 1; FIG.
제2도는 (C) 제1도에 디바이더레지스터에서 내부클럭의 생성을 위한 클럭분주의 데이터레지스터 내용을 나타낸 도면.Fig. 2 (C) shows the data register contents of the clock division for generating the internal clock in the divider register. Fig.
제3도는 본 발명에 따른 GPI0보드의 내부클럭 분주제어방법에 따라 입력포트에서 내부클럭을 사용하는 경우의 제어동작을 설명하는 플로우차트.FIG. 3 is a flow chart illustrating a control operation when an internal clock is used at an input port according to an internal clock division main control method of a GPI0 board according to the present invention;
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019960017331A KR100190856B1 (en) | 1996-05-22 | 1996-05-22 | Inner clock signal dividing control method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019960017331A KR100190856B1 (en) | 1996-05-22 | 1996-05-22 | Inner clock signal dividing control method |
Publications (2)
Publication Number | Publication Date |
---|---|
KR970076175A true KR970076175A (en) | 1997-12-12 |
KR100190856B1 KR100190856B1 (en) | 1999-06-01 |
Family
ID=19459410
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019960017331A KR100190856B1 (en) | 1996-05-22 | 1996-05-22 | Inner clock signal dividing control method |
Country Status (1)
Country | Link |
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KR (1) | KR100190856B1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100553674B1 (en) * | 1999-03-26 | 2006-02-24 | 삼성전자주식회사 | Apparatus for indivisual control of pci bus clock frequency |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110636603A (en) * | 2019-10-22 | 2019-12-31 | 深圳市道通智能航空技术有限公司 | Aircraft time synchronization system and method |
-
1996
- 1996-05-22 KR KR1019960017331A patent/KR100190856B1/en not_active IP Right Cessation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100553674B1 (en) * | 1999-03-26 | 2006-02-24 | 삼성전자주식회사 | Apparatus for indivisual control of pci bus clock frequency |
Also Published As
Publication number | Publication date |
---|---|
KR100190856B1 (en) | 1999-06-01 |
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