KR19980013886A - Clock generator - Google Patents

Abstract

The present invention relates to a clock generator for providing various output clocks for realizing an efficient synchronous network.

The output clock generator of the conventional clock unit has a problem in that it is difficult for the operator to configure the synchronous network and the output clock can not be selected,

In order to solve this problem, the present invention includes an internal clock generator for generating an internal oscillation clock, and an internal oscillation clock generated from the first and second reference input clocks and the internal clock generator to operate as a source of the system clock A first phase-locked loop unit for generating a system clock in phase with the clock signal output from the first clock selection unit; and a second phase-locked loop unit for selecting one of the first and second reference input clocks to output A system clock distributing unit for dividing the system clock output from the first phase lock loop unit; a clock output from the second clock selecting unit and a system clock divided from the system clock distributing unit; A second phase-locked loop / third clock selector for selecting and outputting one of the synchronous clock and the synchronous clock, Second phase-lock loop / 3 consists of a sinhojung one output from the clock selection section parts fourth clock selecting and outputting to an external clock.

Description

Clock generator

FIG. 1 is a block diagram of a clock generator according to the present invention; FIG.

Description of the Related Art [0002]

101: internal clock generator 102: first clock selector

103: first phase locked loop unit 104: second clock selection unit

105: system clock divider 106: second phase-locked loop / third clock selector

107: fourth clock selection unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock unit, and more particularly, to a clock generator for providing various output clocks to realize an efficient synchronous network.

The conventional clock generator has a problem in that it is difficult for an operator to configure a synchronous network and can not select an output clock so that efficiency in implementing a synchronous network is low.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made keeping in mind the above problems occurring in the prior art, and it is an object of the present invention to provide a clock generator for providing various output clocks for realizing an efficient synchronous network.

According to an aspect of the present invention, there is provided a semiconductor memory device comprising: an internal clock generator for generating an internal oscillation clock; a first reference input clock; and an internal oscillation clock generated from the internal clock generator, A first phase-locked loop unit for generating a system clock in phase with the clock signal output from the first clock selection unit; and a second phase- A second clock selector for selecting one of the input clocks and outputting the selected clock, a system clock distributor for dividing the system clock output from the first phase-lock loop, a clock output from the second clock selector, A second phase-locked loop / third clock selector for phase-locking each of the system clocks divided from the clock divider, And a fourth clock selector for outputting a system clock divided from the system clock divider and a signal output from the second phase-locked loop / third clock selector as an external clock.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a block diagram of a clock generator according to the present invention. The internal clock generator 101 generates an internal oscillation clock. The internal clock generator 101 generates first and second reference input clocks RT1 and RT2, A first clock selection unit 102 for selecting one of the internal oscillation clocks INT generated from the clock generation unit 101 to operate as a source of the system clock ST, A first phase locked loop unit 103 for generating a system clock ST in phase with a clock signal output from the first and second reference input clocks RT1 and RT2; A system clock distributor 105 for dividing the system clock ST output from the first phase lock loop unit 103 and a second clock selector 104 for dividing the system clock ST output from the first phase- And the system clock (ST) divided from the system clock divider (105) A second phase-locked loop / third clock selection unit 106 for selecting one of the phase-locked loop and the third phase-locked loop / And a fourth clock selection unit 107 for outputting one of the signals output from the third clock selection unit 106 to the external clock OT.

The operation and effect of the present invention configured as described above will now be described by dividing into two parts for generating a system clock (ST) clock and an external clock.

The output of the system clock ST is input to the first and second reference input clocks RT1 and RT2 that are input from the first clock selection unit 102 and the first and second reference input clocks RT1 and RT2, And selects and outputs one of the internal oscillation clocks INT.

Then, the first phase locked loop unit 103 outputs the system clock ST in phase with the clock output from the first clock selection unit 102.

Next, in the process of outputting the output clock OT, first, the second clock selection unit 104 selects one of the first and second reference input clocks RT1 and RT2 and outputs the selected one.

Then, the system clock divider 105 divides and outputs the system clock ST output from the first phase lock loop unit 103.

The second phase-locked loop / third clock selector 106 selects the system clock ST divided from the system clock divider 105 and the clock output from the second clock selector 104, And selects and outputs one of the smooth clocks synchronized with each other through the second phase-locked loop.

Therefore, the fourth clock selection unit 107 selects one of the signals output from the second phase-locked loop / third selection unit 106 and the system clock ST divided from the system clock divider 105, And outputs it to the clock OT.

In this case, all of the selection and output are performed by the operator in a software manner, and the operator can easily and easily perform various and efficient operations in implementing the synchronous network by selecting the system clock and output clock of the corresponding equipment in the synchronous network To be able to do it.

As described above, according to the present invention, since the operator can select various clocks, it is possible to implement an efficient synchronous network.

Claims (1)

An internal clock generator 101 for generating an internal oscillation clock, And selects one of the first and second reference input clocks RT1 and RT2 and the internal oscillation clock INT generated by the internal clock generator 101 to operate as the source of the system clock ST, 1 clock selection unit 102, A first phase lock loop unit 103 for generating a system clock signal ST in phase with a clock signal output from the first clock selection unit 102, A second clock selection unit 104 for selecting and outputting one of the first and second reference input clocks RT1 and RT2, A system clock divider 105 for dividing the system clock ST output from the first phase lock loop unit 103, A second phase-locked loop / phase-locked loop (PLL / PLL) 106 for phase-locking the clock output from the second clock selector 104 and the system clock signal ST divided by the system clock divider 105, 3 clock selection unit 106, And a fourth clock selection circuit for outputting a system clock ST divided from the system clock divider 105 and a signal output from the second phase-locked loop / third clock selector 106 as an external clock OT, (107). ≪ Desc / Clms Page number 19 >