JPH0741229Y2 - AMI clock creation circuit - Google Patents

Description

[Detailed description of the device] [Industrial application] The present invention is an AMI in which a 64 kHz component and an 8 kHz component are synthesized.
(Alternate Mark Inversion) A clock signal generating circuit can be applied to, for example, a primary group interface device in ISDN (Integrated Services Digital Network).

[Prior Art] The position of the primary interface device on the data communication system is as shown in FIG. In FIG. 2, the exchange 1 is connected to a network 3 via a network terminating device (NT) 2. The exchange 1 includes an exchange switch (SW) 4, a primary group interface device (PRI) 5, and a system clock generation circuit 6. The primary-group interface device 5 is interposed between the exchange switch 4 and the network terminating device 2 to match the phase and speed of the data from the network 3 to the phase and speed of the data of the exchange switch 4, or vice versa. The phase and speed of data from the network are matched with the phase and speed of data on the network 3, and interface processing is performed. The system clock generation circuit 6 is composed of, for example, a PLL (Phase Locked Loop) circuit, and generates a clock signal that is subordinately synchronized with the network 3 and applies it to the exchange switch 4 to realize a synchronized exchange process. The system clock generation circuit 6 is given a 64 kHz + 8 kHz AMI clock signal from the primary group interface device 5, and forms a clock signal for the exchange switch 4 based on this.

Note that, for example, 1.
It is conceivable to extract the 544 MHz clock signal component and give it to the system clock generation circuit 6, but in reality, the transmission path length between the primary group interface device 5 and the clock generation circuit 6 is long, and phase shift or the like occurs in this transmission. Because of the possibility of occurrence, a relatively low-speed AMI clock signal that is resistant to phase shift is supplied from the primary group interface device 5 to the system clock generation circuit 6.

As shown in FIG. 3, the conventional primary-group interface device 5 used in this way has a signal receiving unit (RCV) 10, a clock extraction timing circuit (TIMG: tuning circuit) 11, and an elastic memory (ESMEM) 12 And 64kHz + 8kHz AMI clock generation circuit 13. 1.54 received by the signal receiver 10
4 Mbps primary group digital multiplexed signal timing circuit 1
1.The clock signal of 1.544MHz included in the signal is extracted to the elastic memory 12 and 64kHz.
+ 8kHz given to AMI clock creation circuit 13.

The ilastic memory 12 converts the speed and phase of the received signal so as to match the exchange switch 4 through the write operation and the read operation using the 1.544 MHz clock signal, and gives the converted switch 4 the same.

On the other hand, the 64 kHz + 8 kHz AMI clock creating circuit 13 creates a 64 kHz + 8 kHz AMI clock signal based on this clock signal and supplies it to the system clock generating circuit 6 described above.

That is, in the AMI clock creating circuit 13, the extracted clock signal of 1.544 MHz is divided into 1/193 by the 1/193 frequency dividing circuit 20 to create an 8 kHz pulse signal, and this pulse signal is generated. It is an integer multiple of 64kHz, for example 16.384MHz
VCO (Voltage Controlled Oscillat)
or)) 21a, which is input to the PLL circuit 21, and this PLL circuit 2
64kHz and 8kHz clock signals are created by dividing the clock signal output from 1 by the divider circuit 22,
After that, the AMI clock signal in which the 64 kHz component and the 8 kHz component were synthesized was created through the unipolar / bipolar conversion circuit (U / B) 23.

[Problems to be Solved by the Invention] However, according to the primary group interface device 5 described above, in addition to the system clock generation circuit 6 of the PLL circuit configuration, the PLL circuit 21 is provided in the 64 kHz + 8 kHz AMI clock generation circuit 13. There is. These have different installation locations and oscillating frequencies, but realize the same function of forming an output clock signal (pulse signal) that follows the primary group digital multiplexed signal from the network 3. Therefore, if the PLL circuit 21 in the AMI clock creation circuit 13 can be omitted,
It is considered to be advantageous in terms of mounting area and material cost.

By the way, no PLL circuit is provided in the circuit that creates the AMI clock signal from the 2.048 MHz clock signal. Considering the polarity change period, etc., it is not possible to form pulse signals of 64 kHz and 8 kHz components even if the clock signal of 1.544 MHz is divided, whereas if the clock signal of 2.048 MHz is divided, This is because it is possible to form That is, in the case of a clock signal of 1.544 MHz, it was necessary to convert the frequency using a PLL circuit and then divide the frequency.

The present invention has been made in consideration of the above points, and 1.
64kHz + 8kHz A from 544Mbps primary group digital multiplexed signal
It is an object of the present invention to provide an easy and small AMI clock generation circuit that can generate an MI clock signal without using a PLL circuit.

[Means for Solving the Problems] In order to solve the above problems, in the present invention, 1.54
1.544 extracted from 4Mbps primary group digital multiplexed signal
AMI that creates a 64kHz + 8kHz AMI clock signal in which 64kHz and 8kHz components are combined from a MHz clock signal
The clock generation circuit was constructed by the following means.

That is, the AMI clock generation circuit uses 193 pulses for every 193 pulses of the 1.544 MHz clock signal.
Pulse number conversion means for converting into 192 pulses within the period including the number of pulses, and the pulse signal output from the pulse number conversion means is divided to generate a plurality of pulse signals having different division ratios. The frequency dividing means to be formed and a plurality of pulse signals output from the frequency dividing means are logically operated to form two pulse signals for specifying the positive and negative periods of the AMI clock signal, and then based on these pulse signals. 64kHz + 8
It consists of a unipolar / bipolar converter that creates a kHz A MI clock signal.

[Operation] In the present invention, the pulse number conversion means is input 1.
193 pulses of the 544 MHz clock signal were converted into 192 pulses within the period including 193 pulses and given to the frequency dividing means, which was output from this pulse number converting means. The pulse signal is frequency-divided to form a plurality of pulse signals having different frequency division ratios, which are given to the unipolar / bipolar converting means. The unipolar / bipolar converting means logically outputs the plurality of pulse signals output from the frequency dividing means. Calculate
After forming two pulse signals that specify the positive and negative periods of the AMI clock signal, based on these pulse signals
Create a 64kHz + 8kHz AMI clock signal.

Here, the reason for providing the pulse number conversion means is that
If the 1.544MHz clock signal is directly divided,
This is because it is not possible to obtain, as the number of divided pulses in one cycle of the 64 kHz component or 8 kHz component of the AMI clock signal, the number corresponding to the number of times of polarity change.

Embodiment An embodiment of the present invention will be described in detail below with reference to the drawings. Here, FIG. 1 is a block diagram showing the configuration of this embodiment, and FIG. 4 is a timing chart of each part thereof. Note that FIGS. 4 (A) to (E) and FIGS. 4 (F) to (M) are shown with different time axes.

In FIG. 1, a 1.544 MHz clock signal CK synchronized with the network extracted from the 1.544 Mbps primary group digital multiplexed signal received by a timing circuit (not shown) (see FIG. 3).
(FIG. 4 (A)) is given to the input terminal 31 of the AMI clock generation circuit 30. The clock signal CK input from the input terminal 31 is supplied to the 1/193 frequency dividing circuit 32 and the 2-input OR circuit 33.

The 1/193 frequency divider circuit 32 is a 4-bit counter circuit 32a and 32b.
And an inverter circuit 32c and 32d,
An 8-bit counter circuit is configured by the two 4-bit counter circuits 32a and 32b, "63" is loaded to the 8-bit counter circuit, and a carry signal (count value "256") is output from the 8-bit counter circuit. By reloading when output, 193 (= 2
56-63) forms a significant pulse signal PL1 (FIG. 4 (B)) for every one clock cycle. This divider circuit 3
The output pulse signal PL1 from 2 is also given to the OR circuit 33.

Since the rising edge of the input clock signal CK and the rising edge of the output pulse signal PL1 of the frequency dividing circuit 32 are synchronized,
One pulse of the input clock signal CK is included in the significant period of the output pulse signal PL1, and from the OR circuit 33, a pulse signal obtained by converting 193 pulses of the input clock signal CK into 192 pulses, that is, A pulse signal PL2 (FIG. 4 (C)) obtained by removing one pulse is output for every 193 input clock signals.

Here, the time including 193 pulses of the input clock signal CK is 125 μs, and this time is one cycle of 8 kHz.
Therefore, the OR circuit 33 sets the number of pulses in one cycle of 8 kHz to 19
You have two.

The output pulse signal PL2 from the OR circuit 33 is given to the 1/3 frequency divider circuit 34. The frequency dividing circuit 34 is composed of two D-type flip-flop circuits 34a and 34b and a two-input NOR circuit 34c. The output pulse of the OR circuit 33 is applied to the clock input terminals of the flip-flop circuits 34a and 34b. The signal PL2 is input, and the non-inverting output terminal of the flip-flop circuit 34a is connected to the data input terminal of the flip-flop circuit 34b and the NOR circuit 34c.
To the input terminal of the flip-flop circuit 34b, the non-inverting output terminal of 34b of the flip-flop circuit 34b is connected to the input terminal of the NOR circuit 34c, and the output terminal of the NOR circuit 34c is connected to the data input terminal of the flip-flop circuit 34a. The output pulse signal PL3 (Fig. 4 (D)) is taken out from the non-inverting output terminal of the circuit 34b.

Thus, from the frequency divider circuit 34, one out of every three output pulse signals PL2 of the OR circuit 33 and a significant pulse signal PL3 is output during one cycle (may be different) of the input clock signal CK. To be done.

Therefore, the frequency dividing circuit 34 reduces the number of pulses in one cycle of 8 kHz to 64.
You are making it into an individual.

The output pulse signal PL3 of the frequency dividing circuit 34 is the frequency dividing circuit 3 having three outputs.
Given to 5. This frequency dividing circuit 35 is composed of a 7-ary counter circuit, and divides the output pulse signal PL3 of the frequency dividing circuit 34 into 1/4 pulse signals PL4 (FIG. 4 (F): Q2 output of the counter), 1 Pulse signal PL5 divided by / 8 (Fig. 4 (G): Q3 output of the counter) and pulse signal PL6 divided by 1/64
(FIG. 4 (J): Q6 output of counter) A total of three divided pulse signals are output.

Here, the 1/4 frequency-divided pulse signal PL4 specifies the polarity period of the AMI clock signal regardless of whether the polarity is positive or negative. The 1/8 frequency-divided pulse signal PL5 is for switching between the positive electrode and the negative electrode. The 1/64 frequency-divided signal PL6 is for forming an 8 kHz component of the AMI clock signal, and has two cycles of 8 kHz as a cycle.

For reference, FIG. 4 also shows other outputs Q0, Q4, and Q5 of the counter that constitutes the frequency dividing circuit 35.

These divided pulse signals PL4 to PL6 are supplied to the unipolar / bipolar conversion circuit 36. The conversion circuit 36 includes a 2-input exclusive OR circuit 36a and an inverter circuit 36.
b, two NAND circuits 36c and 36d, pull-up resistors 36e and 36f of each NAND circuit, and a transformer 36g.

The exclusive OR circuit 36a has a 1/8 divided pulse signal.
The PL5 and the 1/64 frequency-divided pulse signal PL6 are input, and thus the polarity of the start is switched every 1 cycle of 8 kHz, and the pulse signal instructing to alternately change the polarity within the cycle is output. This pulse signal is the inverter circuit
The signal is inverted via 36b and given to the NAND circuit 36c, and also directly given to the other NAND circuit 36d.

As a result, the NAND circuit 36c outputs the pulse signal PL7 (FIG. 4 (K)) that specifies the period in which the AMI clock signal has the positive polarity at the logic "L" level, and the NAND circuit 36d outputs the pulse signal PL7.
A pulse signal PL8 (FIG. 4 (L)) that specifies the period in which the AMI clock signal has a negative polarity at the logic "L" level is output.

The output terminals of the NAND circuits 36c and 36d are connected to both ends of the primary winding of the transformer 36g. Therefore, when the output PL7 of the NAND circuit 36c is logic "L", a current flows from the NAND circuit 36d to the NAND circuit 36c, and the AMI clock signal CKOUT (the fourth level) of the positive level is output from the secondary winding of the transformer 36g. (M)) is output, and conversely, when the output PL8 of the NAND circuit 36d is logic "L", the NAND circuit 36d
A current flows from 36c toward the NAND circuit 36d, and the AMI clock signal CKOU at the negative level is output from the secondary winding of the transformer 36g.
T is output, and outputs PL7 and PL8 of NAND circuits 36c and 36d
Are both logic "H", no current flows through the transformer 36g and the 0 level AMI clock signal CKOUT is output.

In this way, the transformer 36g outputs the 64 kHz + 8 kHz AMI clock signal CKOUT, which is applied to the system clock generating circuit (not shown) (see FIG. 2).

A 1/193 frequency divider 32 and an OR circuit 33 are provided to provide 8kHz
The number of pulses in one cycle of is set to 192,
The reason is as follows. As shown in Fig. 4 (M), 64kHz
For the + 8kHz AMI clock signal CKOUT, the level must be changed 16 times during one cycle of 8kHz. Therefore, when the AMI clock signal CKOUT is created while dividing the input clock signal CK, it is necessary to use 16 integer multiple pulses of the input clock signal CK. Here, the number of pulses in one cycle of 8 kHz is 193, which is not an integral multiple of 16. The nearest multiple of 16 to this number is
It is 192. Therefore, we decided to create the AMI clock signal CKOUT from 192 pulses. Here, when 192 pulses of the input clock signal CK are directly used, the number of pulses in one cycle is 193, so the cycle of the created AMI clock signal is deviated from the original cycle. Therefore, the 1/193 frequency dividing circuit 32 and the OR circuit 33 are provided so that the number of pulses is 192 while the length of one cycle of 8 kHz is secured. As a result, it is possible to create the AMI clock signal CKOUT while keeping the period of one cycle as the original length.

By doing so, one period (t2) out of 16 level change periods of the AMI clock signal in one cycle of 8 kHz.
Is longer than other periods (t1). However, since the system clock generation circuit is provided with the PLL circuit, the PLL circuit absorbs such a period variation and does not pose a practical problem.

Therefore, according to the above-described embodiment, the AMI clock generation circuit 30 can be realized by combining the logic circuits without using the PLL circuit, and the overall configuration of the circuit can be simplified and miniaturized.

Although the present invention is applied to the AMI clock generation circuit in the primary interface device in the above-described embodiment, the present invention is not limited to this.
It can be widely applied to a creation circuit that creates a 64kHz + 8kHz AMI clock signal from a 1.544MHz clock signal.

Further, the specific configuration of each frequency dividing circuit is not limited to that of the above embodiment.

[Effects of the Invention] As described above, according to the present invention, since it is configured by combining the logic circuits, it is possible to realize a simple and compact AMI clock generation circuit as compared with the conventional circuit using the PLL circuit. .

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an AMI clock generation circuit according to the present invention, FIG. 2 is a block diagram explaining the system position of a primary group interface device in which the AMI clock generation circuit is used, and FIG. FIG. 4 is a block diagram showing a detailed structure of a primary group interface device including a conventional AMI clock generation circuit, and FIG. 4 is a timing chart of each part of the above embodiment. 30 …… AMI clock generation circuit, 32 …… 1/193 frequency divider, 33
…… OR circuit, 34 …… 1/3 divider circuit, 35 …… 3-output divider circuit, 36 …… Unipolar / bipolar converter circuit.

Claims (1)

[Scope of utility model registration request] 1. An AMI clock generation circuit for generating a 64 kHz + 8 kHz AMI clock signal in which a 64 kHz component and an 8 kHz component are synthesized from a 1.544 MHz clock signal extracted from a 1.544 Mbps primary group digital multiplexed signal, Every 193 pulses of the clock signal of
Pulse number conversion means for converting one pulse into 192 pulses within a period including 193 pulses, and dividing the pulse signal output from this pulse number conversion means to obtain different division ratios. Frequency dividing means for forming a plurality of pulse signals and a plurality of pulse signals outputted from the frequency dividing means are logically operated to form two pulse signals for specifying the positive and negative periods of the AMI clock signal, A unipolar / bipolar conversion means for generating a 64 kHz + 8 kHz AMI clock signal based on these pulse signals is provided.
AMI clock creation circuit.