JP4678109B2 - Clock generating apparatus and method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
In particular, the present invention generates an audio master clock having a frequency of 12.288 MHz synchronized with the system clock from a system clock (STC) of MPEG (Moving Picture Coding Experts Group) 2-TS (Transport Stream) having a frequency of 27 MHz. The present invention relates to a clock generation apparatus and method suitable for use in the above.
[0002]
[Prior art]
Japanese digital satellite broadcasting is based on ARIB (Association of Radio Industrial and Businesses) standards. The ARIB standard is created based on the European DVB (Digital Video Broadcasting) standard, and broadcasts video and audio in an MPEG2-TS system.
[0003]
MPEG2-TS is assumed to be applied to environments where data transmission errors occur, such as broadcasting and communication networks, and since a plurality of programs can be configured in one stream, digital satellite broadcasting It is used for such as.
[0004]
In this MPEG2-TS, a plurality of 188-byte fixed-length TS packets are collected to form a TS stream. The length of the 188-byte TS packet is determined in consideration of consistency with the ATM (Asynchronous Transfer Mode) cell length.
[0005]
A TS packet includes a 4-byte fixed-length packet header, a variable-length adaptation field, and a payload. In the packet header, PID (packet identifier) and various flags are defined. The type of TS packet is identified by this PID.
[0006]
A PES (Packetized Elementary Stream) packet containing individual streams such as video and audio is divided into a plurality of TS packets having the same PID number and transmitted. For example, the MPEG2 system is used for video encoding. For example, MPEG2-AAC (MPEG2 Advanced Audio Coding) is used for encoding audio in digital BS (Broadcast Satellite) broadcasting. Also, the PES packet in which data such as captions is stored is divided into a plurality of TS packets and transmitted, like the video and audio packets.
[0007]
In such MPEG2-TS, a PCR (Program Clock Reference) is sent every predetermined time in order to adjust the time of STC (System Time Clock).
[0008]
That is, some TS packets include an adaptation field. The adaptation field is used to transmit additional information related to the individual stream. Here, a 6-byte PCR is arranged in the optional field.
[0009]
On the receiver side, the 27 MHz STC which is the system clock is counted by the STC counter. The time of this STC counter is compared with the time of PCR, and thereby a VCO (Voltage Controlled Oscillator) that generates STC is controlled. Thereby, the time of STC is calibrated based on the time of PCR.
[0010]
[Problems to be solved by the invention]
In such digital BS broadcast and digital CS broadcast receivers, video and audio decoding processing is performed in synchronization with the STC clock.
[0011]
For example, 48 kHz is used as a sampling frequency of audio data, and a clock of 12.288 MHz (48 kHz × 256 = 12.2288 MHz) which is 256 times this is used as an audio master clock. Therefore, it is necessary to form an audio master clock having a frequency of 12.288 MHz synchronized with the STC.
[0012]
That is, FIG. 4 shows an outline of audio processing of a receiver for digital BS broadcasting or digital CS broadcasting.
[0013]
In FIG. 4, an STC having a frequency of 27 MHz synchronized with PCR is supplied from the input terminal 101 to the audio clock generation circuit 102. The audio clock generation circuit 102 generates an audio master clock synchronized with the STC.
The frequency of this audio master clock is, for example, (48 kHz × 25 = 12.2288 MHz) when the audio sampling clock is 48 kHz. This audio master clock is supplied to an audio DSP (Digital Signal Processor) 103.
[0014]
The audio DSP 103 operates with this audio master clock. The audio DSP 103 performs decoding processing of the digital audio signal and various signal processing on the digital audio signal.
[0015]
The audio DSP 103 outputs a word clock, a bit serial clock, and PCM (Pulse Code Modulation) data. The output of the audio DSP 103 is supplied to a D / A (Digital to Analog) converter 104. The D / A converter 104 converts the digital audio data into an analog audio signal. The left and right analog audio signals are output from the audio output terminals 105A and 105B.
[0016]
As described above, in order to process an audio signal, a digital BS broadcast or digital CS broadcast receiver needs to generate an audio master clock having a frequency of 12.288 MHz synchronized with an STC having a frequency of 27 MHz.
[0017]
However, the relationship between the STC frequency of 27 MHz and the audio master clock frequency of 12.288 MHz is not a simple integer ratio. For this reason, the master clock of audio data cannot be generated by simply dividing the STC clock by the frequency divider.
[0018]
When generating clocks having two different frequencies synchronized with each other, as shown in FIG. 5, an analog clock composed of counters 111 and 112, a phase comparator 113, a loop filter 114, and a VCO (Voltage Controlled Oscillator) 115 is used. A PLL (Phase Locked Loop) is generally used.
[0019]
However, when the clock generator is composed of an analog PLL, the following problems occur.
[0020]
First, when such a PLL circuit is realized by an integrated circuit, variations in characteristics occur due to problems inherent in the manufacture of the integrated circuit. Therefore, it is necessary to devise measures to compensate for this, and the design is not easy. . In addition, it is necessary to devise a circuit in order to maintain the tolerance against malfunction caused by the fluctuation of the input frequency system. In addition, a design with temperature compensation in mind is required.
[0021]
Further, if the audio clock generator is not mounted in the apparatus as an independent device but is desired to be mounted as a part of another integrated circuit, a clock generator using an analog PLL is necessarily provided due to these problems. It is not easy.
[0022]
Therefore, an object of the present invention is to synchronize with the first frequency clock with a simple configuration even when the frequency relationship between the first frequency clock and the second frequency clock is not a simple integer ratio. It is an object of the present invention to provide a clock generation apparatus and method capable of generating a clock having a second frequency.
[0023]
[Means for Solving the Problems]
The present invention comprises a counting means for inputting a first clock having a frequency f1 and counting the number of first clocks;
Decoding means for decoding the count value of the counting means and outputting a second clock of frequency f2 synchronized with the input clock of frequency f1,
When the frequency f1 of the first clock is greater than the frequency f2 of the second clock and the frequency f1 is not divisible by the frequency f2, the decoding means
A frequency-divided output of a natural number P having a relationship of (P <f1 / f2) and a frequency-divided output of a natural number Q satisfying (f1 / f2 <Q) are combined in a predetermined pattern and synchronized with the first clock. Generate 2 clocks
This is a clock generator as described above.
[0024]
The present invention relates to a clock generation method for generating a second clock having a frequency f2 synchronized with a first clock from a first clock having a frequency f1.
When the frequency f1 of the first clock is greater than the frequency f2 of the second clock and the frequency f1 is not divisible by the frequency f2,
A frequency-divided output of a natural number P having a relationship of (P <f1 / f2) and a frequency-divided output of a natural number Q satisfying (f1 / f2 <Q) are combined in a predetermined pattern and synchronized with the first clock. Generate 2 clocks
This is a clock generation method as described above.
[0025]
For example, assume that the first clock is STC, the frequency f1 is 27 MHz, the second clock is the audio master clock, and the frequency f2 is 12.288 MHz. In this relationship, (f1 / f2) is about 2.2, which is not a simple integer ratio.
[0026]
First, a natural number P that satisfies the relationship (P <f1 / f2) and a natural number Q that satisfies (f1 / f2 <Q) are obtained. In this case, since (f1 / f2) is about 2.2, P = 2 and Q = 3.
[0027]
And
f1: f2 = N: M
A natural number N and a natural number M are obtained. In this case, N = 1125 and M = 512.
[0028]
And
N = a × P + b × Q and M = a + b
Therefore, a natural number a and a natural number b that satisfy the above are obtained almost simultaneously. In this case, a = 401 and b = 101.
[0029]
Accordingly, in this case, the STC is frequency-divided in such a pattern that the frequency-divided output is output 401 times and the frequency-divided output is output 101 times. At this time, the pattern is such that the divide-by-2 output and the divide-by-3 output are dispersed. As a result, an audio master clock having a frequency of 12.288 MHz synchronized with the STC having a frequency of 27 MHz can be generated.
[0030]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of the present invention. In this embodiment, an audio master clock having a frequency of 12.288 MHz is generated in synchronization with a clock having a frequency of 27 MHz, which is an MPEG2-TS system clock (STC).
[0031]
In FIG. 1, reference numeral 1 is an 11-bit synchronous counter, and reference numeral 2 is a decoder that generates an output every time the synchronous counter 1 has a predetermined frequency division ratio. The synchronous counter 1 and the decoder 2 are supplied with STC, which is a system clock having a frequency of 27 MHz, from the input terminal 4. This STC is synchronized with the PCR. Also, an asynchronous reset signal is supplied to the input terminal 5, and this asynchronous reset signal is supplied to the synchronous counter 1 and the reset terminal of the decoder 2.
[0032]
The synchronous counter 1 counts STC from the input terminal 4. The count output of the synchronous counter 1 is supplied to the decoders 2 and 3. As shown in FIG. 2, the decoder 2 decodes so that the output of the synchronous counter 1 is divided into two and three in a predetermined pattern.
[0033]
For example, when the output of the synchronous counter 1 is from (0x000h) (h indicates a hexadecimal number) to (0x00ah), the output of the decoder 2 has a pattern of [10101001010], and is divided into [2 divided by 2, divided by 2, 3 minutes] , Divide by two, divide by two, and divide by two].
[0034]
The decoder 3 counts the output of the synchronous counter 1 for a predetermined period (between 0x000h and 0x464h), and when the predetermined count number (0x464h) is reached, the synchronous counter 1 is synchronously reset.
[0035]
The output of the decoder 2 is output from the output terminal 6. From the output signal from the output terminal 6, for example, an audio master clock corresponding to a frequency of 12.288 MHz and synchronized with the system clock (STC) can be obtained.
[0036]
As described above, the configuration including the synchronous counter 1 and the decoders 2 and 3 can generate an audio master clock corresponding to a frequency of 12.288 MHz synchronized with an STC of 27 MHz, for example. This will be described below.
[0037]
The ratio of the STC clock frequency of 27 MHz and the audio master clock frequency of 12.288 MHz is about 2.2, which is not a simple integer ratio. For this reason, a simple frequency dividing circuit cannot generate an audio master clock having a frequency of 12.288 MHz from an STC having a frequency of 27 MHz. An analog PLL increases the circuit scale.
[0038]
Therefore, in the embodiment of the present invention, an STC clock having a frequency of 27 MHz is divided by, for example, a combination of frequency division by 2 and frequency division by 3 to generate an audio master clock of 12.288 MHz. ing.
[0039]
That is, in this example, for the output of the synchronous counter 1, the decoder 2 repeats the set of [divided by 2, divided by 2, divided by 3, divided by 2, divided by 2] seven times, [Divide by 2] and repeat the [Divide by 2, Divide by 2, 3 Divide, Divide by 2, Divide by 2] group 15 times, and then do [Divide by 2] and [Divide by 2] 2 divisions, 3 divisions, 2 divisions, 2 divisions] is repeated 14 times, then [2 divisions] is performed, and [2 divisions, 2 divisions, 3 divisions, 2 divisions] 2 divided] 14 times, then [divided by 2], then [divided by 2, 2 divided, 3 divided, 2 divided by 2] repeated 15 times, Then, [Division by 2] is performed, and the set of [2 division, 2 division, 3 division, 2 division, 2 division] is repeated 14 times, and then [Division by 2] is performed. [Divided, divided by 2, divided by 3, divided by 2, divided by 2, divided by 2] is repeated 15 times, then [divided by 2] And, [divided by 2, divided by 2, 3 divide, divided by two, divide-by-2] sets the divides to repeat seven times and to output.
[0040]
That is, “2” is a notation method representing a frequency division by 2, and “3” is a notation method representing a frequency division by 3. In addition, a notation such as [2 3] represents a case where a pulse corresponding to divide by 3 is output after a pulse corresponding to divide by 2 is output. Furthermore, when expressed as [2 2 3] x N, this outputs a pulse equivalent to divide by 2, then outputs a pulse equivalent to divide by 2, and then outputs a pulse equivalent to divide by 3 It is assumed that this series set is repeated N times. According to this notation, the decoder 2 performs the following frequency division.
[0041]
[2 2 3 2 2] x 7
[2]
[2 2 3 2 2] x 15
[2]
[2 2 3 2 2] x 14
[2]
[2 2 3 2 2] x 14
[2]
[2 2 3 2 2] x 15
[2]
[2 2 3 2 2] x 14
[2]
[2 2 3 2 2] x 15
[2]
[2 2 3 2 2] x 7
[0042]
As a result, the divide by 2 is performed 401 times and the divide by 3 is performed 101 times. Dividing by 2 times is performed 401 times and dividing by 3 times is performed 101 times for a system clock having a frequency of 27 MHz. This is equivalent to the generation of a 12.288 MHz audio master clock.
[0043]
As described above, the clocks having two frequencies that are not in an integer ratio can be pseudo-divided by repeating, for example, a clock divided by 2 and a clock divided by 3 in a predetermined pattern. This will be described below.
[0044]
Now, assuming that the input frequency is f1 and the output frequency is f2, there is a relationship of f1> f2.
[0045]
First, the maximum natural number P that satisfies the relationship (P <f1 / f2) and the minimum natural number Q that satisfies (f1 / f2 <Q) are obtained. In this case, since (f1 / f2) is about 2.2, P = 2 and Q = 3.
[0046]
And
f1: f2 = N: M
A natural number N and a natural number M are obtained. In this case, N = 1125 and M = 512.
[0047]
And
N = a × P + b × Q and M = a + b
Therefore, a natural number a and a natural number b that satisfy the above are obtained almost simultaneously. In this case, a = 401 and b = 101.
[0048]
Accordingly, in this case, the STC is frequency-divided in such a pattern that the frequency-divided output is output 401 times and the frequency-divided output is output 101 times. At this time, the pattern is such that the divide-by-2 output and the divide-by-3 output are dispersed. As a result, an audio master clock having a frequency of 12.288 MHz synchronized with the STC having a frequency of 27 MHz can be generated.
[0049]
Using such parameters, whether to output P frequency division of frequency f1 or Q frequency division of f1 is solved by the following procedure.
[0050]
In FIG. 3, variables are initialized in step S1. In step S2, a reference is calculated. The reference ref is
ref = (1 / f2) * i
As required.
[0051]
In step S3, if a P-divided clock is generated, span SPAN1 is
SPAN1 = (P / f1) * (A + 1) + (Q / f1) * B
As required. In step S4, the difference delta1 between the span SPAN1 and the reference ref is obtained.
[0052]
Or, when the Q-divided clock is generated in step S5, the span SPAN2 is
SPAN2 = (P / f1) * A + (Q / f1) * (B + 1)
As required. In step S6, the difference delta2 between the span SPAN2 and the reference ref is obtained.
[0053]
In step S7, it is determined whether or not the difference delta1 is smaller than the difference delta2 and A is smaller than LIMIT_A.
[0054]
If it is determined in step S8 that the difference delta1 is smaller than the difference delta2 and A is smaller than LIMIT_A in step S5, A is incremented and a P-divided clock is generated.
[0055]
If it is determined in step S9 that the difference delta1 is smaller than the difference delta2 and A is not smaller than LIMIT_A in step S7, whether or not the difference delta1 is larger than the difference delta2 and B is smaller than LIMIT_B. To be judged.
[0056]
If it is determined in step S10 that the difference delta1 is greater than the difference delta2 and B is less than LIMIT_B in step S9, B is incremented and a Q-divided clock is generated.
[0057]
If it is determined in step S11 that the difference delta1 is larger than the difference delta2 and B is not smaller than LIMIT_B in step S9, whether or not the difference delta1 and the difference delta2 are equal and A is smaller than B Is judged.
[0058]
In step S12, when it is determined in step S11 that the difference delta1 and the difference delta2 are equal and A is smaller than B, A is incremented and a P-divided clock is generated.
[0059]
If it is determined in step S13 that the difference delta1 is equal to the difference delta2 and A is not smaller than B in step S11, whether or not the difference delta1 and the difference delta2 are equal and A is greater than B Is judged.
[0060]
In step S14, if it is determined in step S13 that the difference delta1 and the difference delta2 are equal and A is greater than B, B is incremented and a Q-divided clock is generated.
[0061]
If it is determined in step S15 that the difference delta1 and the difference delta2 are equal and A is not greater than B in step S13, it is determined whether B is equal to LIMIT_B and A is less than LIMIT_A. Is done.
[0062]
If it is determined in step S16 that B and LIMIT_B are equal in step S15 and A is smaller than LIMIT_A, A is incremented and a P-divided clock is generated.
[0063]
In step S17, when it is determined in step S15 that B and LIMIT_B are equal and A is not smaller than LIMIT_A, it is determined whether A and LIMIT_A are equal and B is smaller than LIMIT_B. The
[0064]
If it is determined in step S18 that A and LIMIT_A are equal and B is smaller than LIMIT_B in step S17, B is incremented and a Q-divided clock is generated.
[0065]
Steps S8, S10, S12. S14. When A or B is incremented in S16 and S18 and a P-divided clock or a Q-divided clock is generated, i is incremented in step S19. In step S20, (TOTAL + 1) is compared with i. If i is smaller than (TOTAL + 1), the process returns to step S2. The same processing is repeated until i becomes larger than (TOTAL + 1).
[0066]
As described above, P frequency division and Q frequency division are set.
[0067]
As described above, in the embodiment of the present invention, an audio master clock having a frequency of 12.288 MHz is generated from an STC clock having a frequency of 27 MHz. In this case, the divide-by-two clock is 411 and the divide-by-3 clock is 101 in 1125 clocks, and the divide-by-2 and divide-by-3 clocks in the pattern shown in FIG. Are output.
[0068]
That is,
(A) Repeat the set of [divide by two, divide by two, divide by three, divide by two, divide by two] seven times,
(B) Do [divide by 2],
(C) The set of [divided by 2, divided by 2, divided by 3, divided by 2, divided by 2] is repeated 15 times,
(D) Do [divide by two],
(E) It repeats the set of [divided by two, divided by two, divided by three, divided by two, divided by two] 14 times,
(F) Do [divide by 2],
(G) Repeat [14 divided by 2, divided by 2, divided by 3, divided by 2, divided by 2] 14 times,
(H) Do [divide by 2],
(I) The set of [divide by two, divide by two, divide by three, divide by two, divide by two] is repeated 15 times,
(J) Do [divide by 2]
(K) Repeat [14 divided by 2, divided by 2, divided by 3, divided by 2, divided by 2] 14 times
(L) Do [divide by 2],
(M) Repeat the set of [divide by two, divide by two, divide by three, divide by two, divide by two] 15 times,
(N) Do [divide by 2]
(O) Repeat [7 divided by 2, divided by 2, divided by 3, divided by 2, divided by 2] seven times.
[0069]
FIG. 2 shows the output of the decoder 2 when an output having such a frequency division ratio is obtained.
[0070]
First, corresponding to (A), when the clock count is “0x000” to “0x04c” in hexadecimal notation, [divide by 2, divide by 2, divide by 3, divide by 2, divide by 2,] As shown, the pattern in which [10101001010] is output is repeated seven times.
[0071]
Corresponding to (B), when the clock count is “0x04d” to “0x04e” in hexadecimal notation, “10” is output so as to be [divided by 2].
[0072]
Corresponding to (C), when the clock count is from “0x04f” to “0x0f3” in hexadecimal notation, it will be [divided by 2, divided by 2, divided by 3, divided by 2, divided by 2] In addition, the pattern in which [10101001010] is output is repeated 15 times.
[0073]
Corresponding to (D), when the clock count is “0x0f4” to “0x0f5” in hexadecimal notation, “10” is output so as to be [divided by 2].
[0074]
Corresponding to (E), when the clock count number is “0x0f6” to “0x18f” in hexadecimal notation, it is [divided by 2, divided by 2, divided by 3, divided by 2, divided by 2] In addition, the pattern in which [10101001010] is output is repeated 14 times.
[0075]
Corresponding to (F), when the clock count is “0x190” to “0x191” in hexadecimal notation, “10” is output so as to be [divided by 2].
[0076]
Corresponding to (G), when the clock count is from “0x192” to “0x22b” in hexadecimal notation, it will be [divided by 2, divided by 2, divided by 3, divided by 2, divided by 2] In addition, the pattern in which [10101001010] is output is repeated 14 times.
[0077]
Corresponding to (H), when the clock count is “0x22c” to “0x22d” in hexadecimal notation, “10” is output so as to be [divided by 2].
[0078]
Corresponding to (I), when the clock count is from “0x22e” to “0x2d2” in hexadecimal notation, it will be [divided by 2, divided by 2, divided by 3, divided by 2, divided by 2] In addition, the pattern in which [10101001010] is output is repeated 15 times.
[0079]
Corresponding to (J), when the clock count is “0x2d3” to “0x2d4” in hexadecimal notation, “10” is output so as to be [divided by 2].
[0080]
Corresponding to (K), when the clock count is from “0x2d5” to “0x36e” in hexadecimal notation, it will be [divided by 2, divided by 2, divided by 3, divided by 2, divided by 2] In addition, the pattern in which [10101001010] is output is repeated 14 times.
[0081]
Corresponding to (L), when the clock count is “0x36f” to “0x370” in hexadecimal notation, “10” is output so as to be [divided by 2].
[0082]
Corresponding to (M), when the clock count is “0x371” to “0x415” in hexadecimal notation, it will be [divided by 2, divided by 2, divided by 3, divided by 2, divided by 2] In addition, the pattern in which [10101001010] is output is repeated 15 times.
[0083]
Corresponding to (N), when the clock count is “0x416” to “0x417” in hexadecimal notation, “10” is output so as to be [divided by 2].
[0084]
Corresponding to (O), when the clock count number is “0x418” to “0x464” in hexadecimal notation, it is [divided by 2, divided by 2, divided by 3, divided by 2, divided by 2]. In addition, the pattern in which [10101001010] is output is repeated seven times.
[0085]
As described above, in the embodiment of the present invention, for example, the first clock is the STC, the frequency f1 is 27 MHz, the second clock is the audio master clock, and the frequency f2 is 12.288 MHz. When the simple integer ratio is not obtained, the STC is divided in such a pattern that the divided-by-2 output is output 401 times and the divided-by-3 output is output 101 times. As a result, an audio master clock having a frequency of 12.288 MHz synchronized with the STC having a frequency of 27 MHz can be generated.
[0086]
In the above-described example, the case where the audio master clock is generated from the STC has been described. However, the present invention can be similarly applied when generating clocks that need to be synchronized with each other.
[0087]
【The invention's effect】
According to the present invention, it is not a simple integer ratio from the case of the first clock of frequency f1, as in the case of generating the audio master clock of frequency 12.288 MHz from the STC clock of frequency 27 MHz. When generating the second clock of frequency f2, first, a natural number P having a relation of (P <f1 / f2) and a natural number Q of (f1 / f2 <Q) are obtained, and
f1: f2 = N: M
Natural number N and natural number M are obtained, and
N = a × P + b × Q and M = a + b
Therefore, a natural number a and a natural number b that satisfy the above are obtained almost simultaneously. Then, the first clock is divided in such a pattern that the P-divided output is output a times and the Q-divided output is output b times. Thereby, a second clock having a frequency f2 synchronized with the first clock having a frequency f1 can be generated.
[0088]
For example, when an audio master clock having a frequency of 12.288 MHz is generated from an STC clock having a frequency of 27 MHz, the STC has a pattern in which the divided-by-2 output is output 401 times and the divided-by-3 output is output 101 times. Divided.
[0089]
According to the present invention, a clock that does not have a simple integer ratio relationship can be generated by the counter and the decoder, and the circuit scale can be realized as compared with the case of using an analog PLL.
[0090]
Further, according to the present invention, since only a synchronous digital circuit is used, a target clock can be generated without being influenced by variations caused at the time of manufacture. In addition, there is an advantage that no malfunction occurs due to the fluctuation of the input clock. Furthermore, design considerations for temperature compensation are not required, and integration into an integrated circuit is easy.
[Brief description of the drawings]
FIG. 1 is a block diagram of an embodiment of the present invention.
FIG. 2 is a schematic diagram used for explaining an embodiment of the present invention.
FIG. 3 is a flowchart used to describe an embodiment of the present invention.
FIG. 4 is a block diagram used for explaining an audio master clock synchronized with a system clock.
FIG. 5 is a block diagram used for explaining a conventional clock generation circuit;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Synchronous counter, 2, 3 ... Decoder, 4 ... System clock input terminal, 6 ... Audio master clock output terminal

Claims (7)

Counting means for inputting a first clock of frequency f1 and counting the first clock number;
Decoding means for decoding the count value of the counting means and outputting a second clock having a frequency f2 synchronized with the input clock having the frequency f1,
When the frequency f1 of the first clock is greater than the frequency f2 of the second clock and the frequency f1 is not divisible by the frequency f2,
A natural number P frequency division output having a relation of (P <f1 / f2) and a natural number Q frequency division output of (f1 / f2 <Q) are combined in a predetermined pattern and synchronized with the first clock. A clock generator configured to generate the second clock. The decoding means obtains a natural number P having a relationship of (P <f1 / f2) and a natural number Q satisfying (f1 / f2 <Q),
f1: f2 = N: M
To obtain a natural number N and a natural number M,
N = a × P + b × Q and M = a + b
To obtain a natural number a and a natural number b satisfying
2. The clock generator according to claim 1, wherein the P-divided output is output a times and the Q-divided output is output b times. The clock generator according to claim 1, wherein the P-divided output and the Q-divided output are distributed. The clock generator according to claim 1, wherein the first clock is a system clock, and the second clock is an audio master clock. The clock generator according to claim 1, wherein the frequency of the system clock is 27 MHz, and the frequency of the audio master clock is 12.288 MHz. In a clock generation method for generating a second clock having a frequency f2 synchronized with the first clock from a first clock having a frequency f1,
When the frequency f1 of the first clock is greater than the frequency f2 of the second clock and the frequency f1 is not divisible by the frequency f2,
A natural number P frequency division output having a relation of (P <f1 / f2) and a natural number Q frequency division output of (f1 / f2 <Q) are combined in a predetermined pattern and synchronized with the first clock. A clock generation method for generating the second clock. A natural number P that satisfies the relationship (P <f1 / f2) and a natural number Q that satisfies (f1 / f2 <Q) are obtained.
f1: f2 = N: M
To obtain a natural number N and a natural number M,
N = a × P + b × Q and M = a + b
To obtain a natural number a and a natural number b satisfying
7. The clock generation method according to claim 6, wherein the P-divided output is output a times and the Q-divided output is output b times.

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