JP2001222339A - Clock signal generator and signal generating device and clock signal generating method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To generate a clock signal whose cyclic fluctuation is small by appropriately dividing an oscillation signal. SOLUTION: A control circuit 14 cyclically switches the division rate of a first divider 13, and divides a signal generated by a reference oscillator 1. The first divider 13 transmits the divided signals to a second divider 15. The second divider 15 divides the signals transmitted from the first divider 13 by a prescribed division rate, and transmits it to a phase comparator 16 as a reference frequency signal. In this case, a phase synchronizing loop is constituted of a phase comparator 16, a loop filter 17, a VCO 18, and a fourth divider 20. The VCO 18 generates a signal with prescribed frequencies corresponding to a reference frequency signal transmitted from the second divider 15 to the phase comparator 16, and transmits it to a third divider 19. The third divider 19 divides a signal transmitted from the VCO 18 by the prescribed division rate, and outputs it as a clock signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal generator for generating a signal having a predetermined frequency, and more particularly, to appropriately generating a clock signal having a frequency different from a divisor of a frequency generated by a reference oscillator. For generating a clock signal.

[0002]

2. Description of the Related Art In electronic equipment, a signal of a predetermined frequency generated by one oscillator may be used for various purposes. For example, in a communication device that performs communication by transmitting and receiving an electromagnetic wave signal, a signal generated by a reference oscillator generates a PLL (Phase Lock) that generates a local oscillation signal.
Loop) circuit and used to generate a reference frequency signal. At the same time, in the communication device, the signal generated by the reference oscillator is used to generate a clock signal for driving each part of the communication device.

FIG. 3 is a diagram showing a configuration of a signal generator for generating a local oscillation signal and a clock signal using a signal of a predetermined frequency generated by a reference oscillator in a conventional communication device, for example. In the signal generator shown in FIG. 3, a signal of a predetermined frequency generated by the reference oscillator 50 is supplied to a frequency divider 51 and a PLL (Phase Locked Loop) circuit 52. Here, the frequency divider 51 generates a clock signal by dividing the signal generated by the reference oscillator 50 at a predetermined frequency division ratio. The PLL circuit 5
2, the loop filter 53, and the VCO 54 constitute a frequency synthesizer, and generate a local oscillation signal based on a signal supplied from the reference oscillator 50. In the signal generator shown in FIG. 3, the frequency division ratio of the frequency divider 51 is an integer ratio, and the oscillation frequency of the reference oscillator 50 is an integral multiple of the frequency of the clock signal.

On the other hand, when the oscillation frequency of the reference oscillator 50 is P
When the frequency is set to be an integral multiple of the maximum frequency of the reference frequency signal generated by the LL circuit 52, the oscillation frequency of the reference oscillator 50 may not be an integral multiple of the frequency of the clock signal. In this case, as shown in FIG. 4, a frequency divider 55 having a plurality of types of frequency division ratios is provided, and the frequency division ratio of the frequency divider 55 is periodically switched by the control circuit 56 to thereby obtain a predetermined frequency. To generate a clock signal.

[0005]

However, when the oscillation frequency of the reference oscillator 50 is set to an integral multiple of the clock signal, the signal generator as shown in FIG. Often the signal will be low frequency.

For example, assume that the frequency of the clock signal generated by the frequency divider 51 is 2048 kHz, the oscillation frequency of the reference oscillator 50 is 20.48 MHz, and the frequency of the local oscillation signal is changed in steps of 500 kHz.

In this case, the frequency divider 51 includes a reference oscillator 50
The clock signal can be generated by dividing the frequency of the signal generated by the above into 1/10.

However, in order to compare the phase of the local oscillation signal with the phase of the reference frequency signal in the PLL circuit 52, the signal generated by the reference oscillator 50 is divided so that the maximum reference frequency becomes 20 kHz. There must be. This is because the maximum reference frequency in the PLL circuit 52 must be the greatest common divisor of 20.48 MHz and 500 kHz. For this reason, the C / N ratio (Carrier-to-Noise Ratio) of the local oscillation signal is liable to be deteriorated, which causes deterioration of transmission / reception characteristics.

When the frequency division ratio of the frequency divider 55 is periodically switched as in the signal generator shown in FIG. 4, a phase error occurs because the period of the clock signal is not constant.

For example, the frequency of a clock signal required by a device which receives a clock signal from the signal generator shown in FIG. 4 is 2048 kHz, and the oscillation frequency of the reference oscillator 50 is 16
MHz, and the frequency of the local oscillation signal is changed in steps of 500 kHz.

In this case, for example, if the frequency divider 55 can set the frequency division ratio to 7 or 8, the control circuit 56
Switches the frequency division ratio of the frequency divider 55 periodically, with 16 periods of the signal generated by the reference oscillator 50 as one period. That is, the control circuit 56 divides 13 cycles of the signal generated by the reference oscillator 50 by the frequency divider 55 at a division ratio of 8, and divides three cycles of the signal generated by the reference oscillator 50 into three cycles. The frequency divider 55 divides the frequency by a frequency division ratio of 7. Thereby, a clock signal having a frequency of 2048 kHz can be generated.

However, the period when the frequency of the 16 MHz signal is divided by 7 is 437.5 ns (nanosecond), which is different from the period when the frequency is divided by 8 by 500 ns. For this reason, when an error occurs in the phase with respect to the fixed cycle of 2048 kHz, the processing executed at the timing of the clock signal is shifted, and the transmission / reception characteristics are deteriorated.

The present invention has been made in view of the above situation, and has as its object to provide a clock signal generator capable of appropriately performing frequency division.

[0014]

In order to achieve the above object, a clock signal generator according to a first aspect of the present invention periodically switches a plurality of types of frequency division ratios to generate an oscillation having a predetermined frequency. Frequency dividing means for converting the frequency of the oscillating signal to a frequency different from a divisor of the frequency of the oscillating signal by dividing the signal, and a predetermined frequency based on the oscillating signal divided by the frequency dividing means. Clock generating means for generating a clock signal having a frequency of

According to the present invention, a clock signal having a predetermined frequency is generated based on a signal obtained by dividing an oscillation signal having a predetermined frequency by a plurality of frequency division ratios, so that the frequency of the clock signal is reduced. Even if the frequency is different from the divisor of the frequency of the oscillation signal, the clock signal can be generated by appropriately dividing the frequency of the oscillation signal.

More specifically, the frequency dividing means comprises: a first frequency divider for dividing an oscillation signal by a plurality of frequency division ratios; and an oscillation signal divided by the first frequency divider. And a second frequency divider for dividing the frequency by a predetermined frequency division ratio. Accordingly, the second frequency divider can reduce a phase error included in the oscillation signal divided by the first frequency divider, and can appropriately divide the oscillation signal.

It is preferable that the frequency dividing means includes a control circuit for periodically switching a frequency dividing ratio of the first frequency divider. Further, it is preferable that the control circuit switches the frequency division ratio of the first frequency divider at a predetermined timing specified based on the frequency of the oscillation signal and the frequency of the clock signal.

The clock generating means is preferably a phase locked loop for generating a clock signal having a predetermined frequency using the oscillation signal divided by the frequency dividing means as a reference frequency signal. As a result, the fluctuation of the cycle of the clock signal can be suppressed, so that the frequency of the oscillation signal can be appropriately divided.

The clock generation means includes a phase locked loop for generating a second oscillation signal having a predetermined frequency using the oscillation signal divided by the frequency division means as a reference frequency signal, and a clock generated by the phase locked loop. A third frequency divider that divides the second oscillation signal by a predetermined frequency division ratio to generate a clock signal.

According to a second aspect of the present invention, there is provided a signal generating apparatus comprising: an oscillating means for generating an oscillating signal having a predetermined frequency; A first frequency dividing means for dividing the frequency;
A second frequency dividing means for dividing the oscillation signal divided by the frequency dividing means at a predetermined frequency dividing ratio, and using the oscillation signal divided by the second frequency dividing means as a reference frequency signal. Signal generating means for generating a signal having a frequency of the following frequency: a frequency of an oscillation signal generated by the oscillating means and a frequency division ratio of the first frequency dividing means according to a frequency of a signal generated by the signal generating means. And a switching control means for performing a switching operation.

According to the present invention, it is possible to generate a signal having a predetermined frequency by using, as a reference frequency signal, a signal obtained by dividing the oscillation signal generated by the oscillation means by the plurality of frequency division means. This makes it possible to generate a signal having a small cycle fluctuation, and to appropriately divide the oscillation signal.

[0022] The apparatus may further comprise a local oscillation signal generating means for generating a local oscillation signal having a predetermined frequency based on the oscillation signal generated by the oscillation means.

In a clock signal generating method according to a third aspect of the present invention, an oscillation signal having a predetermined frequency is generated, the oscillation signal is frequency-divided by a plurality of frequency division ratios, and then a predetermined frequency is divided. It is characterized in that a clock signal of a predetermined frequency is generated by a phase-locked loop using a frequency-divided oscillation signal as a reference frequency signal as a reference frequency signal.

Furthermore, it is desirable to periodically switch the frequency division ratio when dividing the oscillation signal according to the frequency of the oscillation signal and the frequency of the clock signal.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a signal generating apparatus to which a clock signal generator according to an embodiment of the present invention is applied will be described in detail with reference to the drawings.

FIG. 1 is a diagram showing a configuration of a signal generator 100 according to an embodiment of the present invention. As shown, the signal generator 100 includes a reference oscillator 1, a local oscillation signal generator 2, and a clock signal generator 3.

The reference oscillator 1 is composed of a crystal oscillator or the like and is for generating a signal of a predetermined frequency.
The reference oscillator 1 supplies the generated signal to the local oscillation signal generator 2 and the clock signal generator 3.

The local oscillation signal generator 2 is a PLL (Phase Locked Loop) frequency synthesizer for generating a local oscillation signal, and includes a PLL circuit 10, a loop filter 11, and a VCO (Voltage Controlled Oscillator) 1.
2 is provided.

The PLL circuit 10 is a one-chip IC (Integer
A programmable frequency divider, a prescaler, a phase comparator, and the like provided on a grated circuit) receive a signal generated by the reference oscillator 1 and a local oscillation signal generated by the VCO 12. The PLL circuit 10 generates a voltage signal according to the difference between the phase of the signal received from the reference oscillator 1 and the phase of the local oscillation signal, and sends the voltage signal to the loop filter 11.

The loop filter 11 is constituted by an LPF (Low Pass Filter) composed of a capacitor, a resistor and the like, and removes a pulse component and a high frequency component of the voltage signal sent from the PLL circuit 10 and supplies the same to the VCO 12. Things.

The VCO 12 is a voltage-controlled oscillator for generating a signal having a frequency corresponding to the voltage signal from which the pulse component and the high-frequency component have been removed by the loop filter 11.
The signal generated by the VCO 12 is output as a local oscillation signal, and is used for a heterodyne local signal and modulation / demodulation of a communication signal. The signal generated by the VCO 12 is sent to the PLL circuit 10.

The clock signal generator 3 is for generating a clock signal from the signal generated by the reference oscillator 1, and includes first to fourth frequency dividers 13, 15, 19, 2
0, a control circuit 14, a phase comparator 16, a loop filter 17, and a VCO 18.

The first frequency divider 13 receives the signal generated by the reference oscillator 1 and divides the signal at a predetermined frequency division ratio. Here, the first frequency divider 13 can divide the signal received from the reference oscillator 1 with at least two kinds, that is, a plurality of kinds of division ratios. First frequency divider 1
The division ratio of 3 is defined by the control circuit 14.

The control circuit 14 is constituted by a microcomputer or the like having a swallow counter, and is for defining the frequency division ratio of the first frequency divider 13. here,
The control circuit 14 periodically switches the frequency division ratio of the first frequency divider 13 to obtain the average frequency division ratio, thereby obtaining the reference oscillator 1
Causes the first frequency divider 13 to generate a signal having a frequency different from the divisor of the oscillation frequency.

The second frequency divider 15 is for dividing the signal sent from the first frequency divider 13 at a predetermined frequency division ratio. The signal divided by the second frequency divider 15 is supplied to the phase comparator 16, the loop filter 17, the VCO 18 and the fourth
Is sent to the phase comparator 16 as a reference frequency signal of the phase locked loop composed of the frequency divider 20 of FIG.

The phase comparator 16 is for generating a voltage signal corresponding to the phase difference between the signal received from the second frequency divider 15 and the signal received from the fourth frequency divider 20. The phase comparator 16 converts the generated voltage signal into a loop filter 17
Send to

The loop filter 17 is composed of an LPF or the like, and removes a pulse component and a high frequency component of the voltage signal sent from the phase comparator 16 and supplies the same to the VCO 18.

The VCO 18 is a voltage controlled oscillator for generating a signal having a frequency corresponding to the voltage signal from which the pulse component and the high frequency component have been removed by the loop filter 17.
The VCO 18 outputs the generated signal to the third frequency divider 19 and the fourth frequency divider 19.
To the frequency divider 20.

The third frequency divider 19 divides the signal sent from the VCO 18 by a predetermined frequency division ratio.
The signal divided by the third divider 19 is, for example, CO
It is supplied as a clock signal to a device for processing a baseband signal, such as a DEC (COder / DECoder).

The fourth frequency divider 20 divides the signal sent from the VCO 18 by a predetermined frequency division ratio.
The fourth frequency divider 20 sends the frequency-divided signal to the phase comparator 16.

The operation of the signal generator 100 according to the embodiment of the present invention will be described below. This signal generator 1
00 is generated by the reference oscillator 1 by the clock signal generator 3 dividing the signal of the predetermined frequency generated by the reference oscillator 1 and then generating a clock signal having a constant period by the phase locked loop. This is a device that can appropriately divide the divided signal.

When the signal generator 100 generates a local oscillation signal and a clock signal, first, the reference oscillator 1
A signal of a predetermined frequency is generated by the oscillation and supplied to the local oscillation signal generator 2 and the clock signal generator 3.

The local oscillation signal generator 2 generates a reference frequency signal using the signal received from the reference oscillator 1 in the same manner as in the prior art, and generates a V signal according to the difference from the phase of the local oscillation signal.
By adjusting the oscillation frequency of the CO 12, a local oscillation signal having a predetermined frequency is generated.

On the other hand, when the clock signal generator 3 receives the signal generated by the reference oscillator 1, first, the first frequency divider 13 divides the frequency by a predetermined frequency division ratio. At this time, the control circuit 14 converts the frequency of the signal received from the reference oscillator 1 to a predetermined frequency by periodically switching the frequency division ratio of the first frequency divider 13.

Here, a certain frequency divider is composed of M and M + 1.
(M: an integer), and a P period of a signal generated by the reference oscillator 1 is defined as (P; an integer) as one period.
It is assumed that the frequency division ratio is switched. The frequency divider divides N periods (N; integer, P ≧ N) of the P periods by a division ratio M + 1.
, And the remaining PN cycles are divided by the division ratio M, the average division ratio Q has the relationship of Equation 1.

## EQU1 ## Q = {(PN) M + N (M + 1)} / P = (PM-NM + NM + N) / P = M + N / P

At this time, G is the greatest common divisor of M and N, and M
= G * m and N = G * n, the average frequency division ratio Q
Can also be expressed as in Equation 2.

## EQU2 ## Q = G (m + n / P)

That is, in order to realize a frequency divider having an average frequency division ratio Q, a frequency divider having a frequency division ratio of m + n / P and a frequency division ratio of G
Should be connected in series.

In the clock signal generator 3, the frequency division ratio of the first frequency divider 13 is set to m or m + 1, and the frequency division ratio is periodically switched by the control circuit 14, and the frequency is divided by the first frequency divider 13. The divided signal is further divided by the second divider 15 having a division ratio of G, whereby a signal having an average division ratio Q can be obtained. Here, the control circuit 14 converts N cycles of the signal generated by the reference oscillator 1 into the first frequency divider 1
3 at the frequency division ratio m, and the PN cycle of the signal generated by the reference oscillator 1 is supplied to the first frequency divider 13 by the frequency division ratio m.
Divide by +1.

As described above, when the control circuit 14 periodically switches the frequency division ratio of the first frequency divider 13, the first frequency divider 1
The signal divided by 3 has a phase error. Therefore, the second frequency divider 15 further divides the signal received from the first frequency divider 13 by a predetermined frequency division ratio to generate a reference frequency signal with a reduced phase error.

The signal divided by the second divider 15 is supplied to a phase comparator 16, a loop filter 17, a VCO 18
And a reference frequency signal of a phase locked loop constituted by the fourth frequency divider 20 and sent to the phase comparator 16.

Phase comparator 16, loop filter 17, V
The CO 18 and the fourth frequency divider 20 operate similarly to a normal phase locked loop. As a result, the VCO 18
A signal synchronized with the reference frequency signal sent from the frequency divider 15 is generated. At this time, since the VCO 18 oscillates at a frequency corresponding to the voltage signal based on the charge accumulated by the filtering by the loop filter 17 having a time constant, the cycle of the output signal when the synchronization is established is kept almost constant. Can be. The VCO 18 sends the generated signal to the third frequency divider 19.

The third frequency divider 19 divides the signal received from the VCO 18 by a predetermined frequency division ratio and supplies it as a clock signal to a device for processing a baseband signal such as CODEC, for example. I do.

In this manner, a clock signal having a low spurious level and a small fluctuation in the period can be generated, and the signal generated by the reference oscillator 1 can be appropriately divided. At this time, the clock signal generator 3
Even when the frequency of the clock signal is different from the divisor of the frequency of the signal generated by the reference oscillator 1, an appropriately divided clock signal can be generated.

For example, the frequency of the clock signal required by the device that receives the clock signal from the clock signal generator 3 is 2048 kHz, and the oscillation frequency of the reference oscillator 1 is 16 MHz.
Hz, and the frequency of the local oscillation signal is changed in steps of 500 kHz.

In this case, the local oscillation signal generator 2 sets the maximum reference frequency to 50, which is the same as the step width of the local oscillation signal.
It can be 0 kHz.

Further, the second frequency divider 15 outputs the phase comparator 1
The frequency (reference frequency) of the signal input to 6 is 1024
kHz, the first frequency divider 13 and the second frequency divider 1
5 is 16 / 1.024 = 5 × (3 + 1
/ 8).

Therefore, by changing the frequency division ratio of the first frequency divider 13 to 3 or 4 and periodically changing the frequency division ratio of the second frequency divider 15 to 5, a desired reference frequency signal can be obtained. Can be generated. At this time, the control circuit 14 controls the reference oscillator 1
Out of eight periods of the signal generated by
, And the remaining seven periods are frequency-divided by the first frequency divider 13 at the frequency division ratio 3.

Assuming that the frequency division ratio of the fourth frequency divider 20 is 10, the VCO 18 is synchronized with the phase of the reference frequency signal input from the second frequency divider 15 to the phase comparator 16. 10. A signal of 10.24 MHz is generated, and the third frequency divider 1
Send to 9. The third frequency divider 19 divides the frequency of the signal received from the VCO 18 by 1/10 to 1024 k
Hz clock signal can be generated.

As described above, according to the present invention,
After the frequency division ratio of the first frequency divider 13 is periodically switched to divide the signal generated by the reference oscillator 1, the second frequency divider 15 further divides the frequency by a predetermined frequency division ratio. Reduce the phase error. The signal frequency-divided by the second frequency divider 15 is input to the phase comparator 16 as a reference frequency signal of a phase locked loop, and the VCO 18 generates a signal synchronized with the reference frequency signal. A clock signal can be generated by appropriately dividing the generated signal.

Further, since the frequency of the signal input to the phase comparator 16 as the reference frequency signal of the phase locked loop can be increased, synchronization can be quickly established. Therefore, for example, as shown in FIG.
Receives the frequency control voltage and AFC (Automatic Freque
ncy Control (automatic frequency control)
The clock signal generator 3 can quickly adjust the frequency of the clock signal according to the frequency of the signal generated by the reference oscillator 1.

Note that the signal generated by the clock signal generator 3 can be used other than the clock signal.
It can also be used as a local oscillation signal.

The clock signal generator 3 has been described as including the third frequency divider 19 and dividing the signal generated by the VCO 18 into a clock signal.
The third frequency divider 19 may be omitted as long as the signal generated by O18 can be supplied as it is as a clock signal.

Further, the clock signal generator 3 uses the first frequency divider 13 and the second frequency divider 15 to
Although it has been described that a signal having a frequency different from the divisor of the frequency of the signal generated by the above is generated, more frequency dividers may be provided to divide the frequency.

[0064]

As described above, according to the present invention, it is possible to appropriately divide a signal having a predetermined frequency and generate a signal such as a clock signal having a small period variation.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a signal generator according to an embodiment of the present invention.

FIG. 2 is a diagram for describing a case where a reference oscillator executes AFC (automatic frequency control).

FIG. 3 is a diagram illustrating an example of a configuration of a conventional signal generator.

FIG. 4 is a diagram showing an example of a configuration of a conventional signal generator.

[Explanation of symbols]

 1,50 Reference oscillator 2 Local oscillation signal generator 3 Clock signal generator 10,52 PLL circuit 11,17,53 Loop filter 12,18,54 VCO 13,15,19,20,51,55 Divider 14, 56 control circuit 16 phase comparator 100 signal generator

Continued on the front page F term (reference) 2F073 AA40 AB07 CC10 CD11 EF10 GG01 5B079 BA03 BB04 BC03 CC13 DD03 DD20 5J106 AA04 CC01 CC20 CC21 CC30 CC38 CC41 CC52 CC53 FF04 FF06 FF09 GG09 HH10 KK12 PP01 QQ05 RR18

Claims (10)

[Claims] 1. A method in which a plurality of types of frequency division ratios are periodically switched,
By dividing the frequency of an oscillation signal having a predetermined frequency,
Frequency dividing means for converting the frequency of the oscillation signal into a frequency different from a divisor of the frequency of the oscillation signal; and generating a clock signal having a predetermined frequency based on the oscillation signal divided by the frequency dividing means. A clock signal generator comprising: 2. A frequency divider comprising: a first frequency divider for dividing an oscillation signal by a plurality of frequency division ratios; a predetermined frequency divider for dividing the oscillation signal by the first frequency divider into a predetermined frequency; The clock signal generator according to claim 1, further comprising: a second frequency divider that divides the frequency by a frequency ratio. 3. The clock signal generator according to claim 2, wherein said frequency dividing means includes a control circuit for periodically switching a frequency dividing ratio of said first frequency divider. 4. The control circuit according to claim 1, wherein the control circuit switches the frequency division ratio of the first frequency divider at a predetermined timing specified based on the frequency of the oscillation signal and the frequency of the clock signal. Item 4. The clock signal generator according to item 3. 5. The clock generating means according to claim 1, wherein said clock generating means is a phase locked loop for generating a clock signal having a predetermined frequency using the oscillation signal divided by said frequency dividing means as a reference frequency signal. Item 5. The clock signal generator according to any one of Items 1 to 4. 6. A phase-locked loop for generating a second oscillation signal having a predetermined frequency using the oscillation signal divided by the frequency divider as a reference frequency signal, wherein: And a third frequency divider for dividing the second oscillation signal generated by the above at a predetermined frequency division ratio to generate a clock signal. 2. The clock signal generator according to 1. 7. An oscillating means for generating an oscillating signal having a predetermined frequency; a first frequency dividing means for dividing the oscillating signal generated by the oscillating means at a plurality of frequency dividing ratios; A second frequency dividing means for dividing the oscillation signal divided by the frequency dividing means by a predetermined frequency dividing ratio; and a predetermined frequency dividing the oscillation signal divided by the second frequency dividing means as a reference frequency signal. Signal generating means for generating a signal having a frequency of the following: a frequency of an oscillation signal generated by the oscillating means and a frequency division ratio of the first frequency dividing means according to a frequency of a signal generated by the signal generating means; And a switching control means for selectively switching. 8. The signal generation device according to claim 7, further comprising a local oscillation signal generation unit that generates a local oscillation signal having a predetermined frequency based on the oscillation signal generated by the oscillation unit. apparatus. 9. An oscillation signal having a predetermined frequency is generated,
After dividing the oscillation signal by a plurality of kinds of division ratios, the frequency is further divided by a predetermined division ratio, and the divided oscillation signal is used as a reference frequency signal to generate a clock signal of a predetermined frequency by a phase locked loop. A method for generating a clock signal, comprising: 10. The clock signal generation method according to claim 9, wherein the frequency division ratio for dividing the oscillation signal is periodically switched according to the frequency of the oscillation signal and the frequency of the clock signal.