JP4651931B2 - Synthesizer - Google Patents

Description

  The present invention relates to a synthesizer that can obtain an output signal synchronized with the phase of an input signal by digital processing.

  Various configurations have already been proposed and put to practical use for obtaining an output signal synchronized with the input signal phase. For example, the basic configuration by analog processing is generally an APLL (analog phase locked loop) shown in FIG. 5, 51 is a phase comparator (PD), 52 is a loop filter (LPF), and 53 is a voltage controlled oscillator. (VCO). In this APLL, an input signal and an output signal are compared by a phase comparator 51, and a phase difference signal between the input signal and the output signal is input as a control voltage of the voltage controlled oscillator 53 via the loop filter 52. The output frequency (output signal phase) of the voltage controlled oscillator 53 is controlled so that the phase difference becomes zero or a predetermined value, and an output signal synchronized with the input signal phase is obtained.

  As a basic configuration by digital processing, a DPLL (digital phase locked loop) shown in FIG. 6 is known. In the figure, 61 is a digital phase comparator (DPD), 62 is a loop filter (LPF), 63 is a direct digital synthesizer (DDS), and 64 is a clock generator (CLK). In this DPLL, an input signal, an output signal, and a clock from a clock generator 64 are input to a digital phase comparator 61, and a clock count value corresponding to the phase difference between the input signal and the output signal is output. The signal is input to the direct digital synthesizer 63 through the loop filter 62.

  This direct digital synthesizer 63 is configured to count up a reference clock (clock from an internal or external clock generator, not shown), and output a signal for each set count value, with a frequency corresponding to the count value. Since it becomes a signal, the phase of the output signal can be controlled by, for example, processing of adding a count value corresponding to the phase difference to the count value, and can be synchronized with the phase of the input signal. Also, since the output signal is a digital signal, when it is a sine wave signal, it is converted by a DA converter and output.

  Further, the DPLL shown in FIG. 7 in which the characteristics of the DPLL shown in FIG. 6 are improved is known. In FIG. 7, 71 is a digital phase comparator (DPD), 72 is a loop filter (LPF), 73 is a direct digital synthesizer (DDS), and 74 is a phase synchronizer (PLL). The phase synchronization unit 74 corresponds to the clock generator 64 in FIG. 6, but is configured to input a clock CLK synchronized with the phase of the output signal to the digital phase comparator 71. Compared with the case where independent clocks are used, the phase detection accuracy is improved.

The output signal phase of a direct digital synthesizer (DDS) with a variable output frequency and the phase of a signal obtained by dividing the output signal of a voltage-controlled oscillator as a local oscillator of a wireless transceiver And a phase comparator, and a synthesizer is known that includes a phase locked loop that controls the output frequency of a voltage controlled oscillator in accordance with the phase difference. (For example, refer to Patent Document 1).
JP-A-6-276096

  For example, the conventional digital phase comparator 61 in the DPLL shown in FIG. 6 is difficult to improve the phase comparison accuracy as compared with the phase comparator 51 in the APLL shown in FIG. In other words, the phase comparison accuracy of the digital phase comparator 61 often depends on the clock frequency. In other words, the phase comparison accuracy is such that one clock is generated as an error. Therefore, in order to reduce this error, the clock frequency should be increased. However, even if the clock frequency is increased, there is an upper limit of the operating frequency according to the circuit configuration and the like, and it is difficult to realize characteristics comparable to those of APLL. Therefore, there is a problem that the tracking characteristic with respect to the input signal phase cannot be improved and noise (jitter) is generated inside.

  Therefore, as shown in FIG. 7, an output signal synchronized with the phase of the input signal is used, and a clock having a frequency sufficiently higher than the output signal frequency is synchronized with the phase of the output signal. A configuration has been proposed in which the (PLL) 74 inputs to the digital phase comparator 71. In this case, unlike the clock from the clock generator 64 in FIG. 6, the phase slightly changes in phase and becomes a dither clock, and the phase comparison timing between the input signal and the output signal Is slightly changed and averaged, so that the accuracy of phase synchronization can be improved.

  In the conventional configuration shown in FIG. 7, it is necessary to realize a slight frequency deviation in order to effectively operate the dither function. For this purpose, the phase synchronization unit (PLL) 74 is Therefore, a minute frequency setting accuracy on the order of several ppm is required. In order to realize such a minute frequency setting accuracy, a large frequency dividing number is required. In the case of downsizing for one chip or the like, the phase synchronization unit 74 uses a voltage controlled oscillator (VCO) having poor noise characteristics. However, since the PLL loop band cannot be widened, the noise is reduced. There is a problem that it is difficult to sufficiently compress the components.

  The present invention solves the above-described problems, and aims to improve the phase comparison accuracy and reduce the noise of the output signal.

A synthesizer of the present invention includes a digital phase comparator that outputs a clock count value corresponding to a phase difference between an input signal and an output signal as a phase comparison output signal, and a loop that inputs the phase comparison output signal of the digital phase comparator filter and a first direct digital which receives the output signal of the loop filter to control the phase of the output signal, and inputs the output signal through a circuit which directly or divider circuit or multiplying said digital phase comparator In a synthesizer including a synthesizer and a phase synchronization unit that generates the clock input to the digital phase comparator, an offset value is added to the output signal of the loop filter and input, and an output signal is output to the phase synchronization unit a second direct digital synthesizer for inputting the first direct digital Singh For frequencies sizer of the output signal, the frequency of the output signal of the second direct digital synthesizer has a frequency difference corresponding to the offset value.

  Also, a digital phase comparator that compares the phase of the input signal and the output signal, a loop filter that inputs the output signal of the digital phase comparator, and an output signal of the loop filter that controls the phase of the output signal A synthesizer including a first direct digital synthesizer that inputs the output signal directly or after frequency division or multiplication to the digital phase comparator, and a phase synchronization unit that generates a clock input to the digital phase comparator. A multiplier for multiplying the output signal of the loop filter by a coefficient and outputting an offset value; a second direct digital synthesizer for adding the offset value and inputting the output signal to the phase synchronization unit; It has.

  Also, a digital phase comparator that compares the phase of the input signal and the output signal, a loop filter that inputs the output signal of the digital phase comparator, and an output signal of the loop filter that controls the phase of the output signal A synthesizer including a first direct digital synthesizer that inputs the output signal directly or after frequency division or multiplication to the digital phase comparator, and a phase synchronization unit that generates a clock input to the digital phase comparator. A pre-filter provided between the digital phase comparator and the loop filter, an offset setting unit that sets an offset value, an offset value that is set in the offset unit is changed every predetermined period, and the A control circuit for inputting the order of the filter corresponding to the offset value to the pre-filter, and the loop filter By adding the offset value from the force signal offset value setting unit type and a second direct digital synthesizer for inputting an output signal to said phase synchronization section.

  Also, a digital phase comparator that compares the phase of the input signal and the output signal, a loop filter that inputs the output signal of the digital phase comparator, and an output signal of the loop filter that controls the phase of the output signal A synthesizer including a first direct digital synthesizer that inputs the output signal directly or after frequency division or multiplication to the digital phase comparator, and a phase synchronization unit that generates a clock input to the digital phase comparator. A pre-filter provided between the digital phase comparator and the loop filter, a multiplier for multiplying the output signal of the loop filter by a coefficient and outputting an offset value, and the coefficient input to the multiplier A control circuit that inputs a filter order corresponding to the coefficient to the prefilter, and a loop Wherein the output signal of the filter by adding the offset value to the input, and a second direct digital synthesizer for inputting an output signal to said phase synchronization section.

  A second direct digital synthesizer that outputs a signal having a frequency difference corresponding to an offset value with respect to the frequency of the output signal of the first direct digital synthesizer is provided, and the output signal of the second direct digital synthesizer is used as a phase synchronization unit. And generating a clock to be input to the digital phase comparator, it is possible to effectively act as a dither clock and to improve the phase detection accuracy. In addition, since the phase synchronization unit that generates the clock can be configured to have a relatively simple multiplication function of an integral multiple, the loop including this phase synchronization unit can be operated at high speed, and the followability to the input signal phase can be improved. It is possible to improve and sufficiently suppress internal noise.

  Referring to FIG. 1, a digital phase comparator 1 that compares the phases of an input signal and an output signal, a loop filter 2 that inputs an output signal of the digital phase comparator 1, and an output of the loop filter 2 A signal is input to control the phase of the output signal, and the output signal is input to the digital phase comparator 1 and a first direct digital synthesizer 3 that is input directly or after being divided or multiplied. In a synthesizer including a phase synchronization unit 5 for generating a clock to be transmitted, an offset value is added to an output signal of the loop filter 2 by an adder 6 and input, and an output signal is input to the phase synchronization unit 5 A direct digital synthesizer 4 is provided.

  FIG. 1 is an explanatory diagram of Embodiment 1 of the present invention, where 1 is a digital phase comparator (DPD), 2 is a loop filter (LPF) by digital processing, 3 is a first direct digital synthesizer (DDS1), 4 Denotes a second direct digital synthesizer (DDS2), 5 denotes a phase synchronization unit (PLL), and 6 denotes an adder.

A digital phase comparator 1 that outputs a clock count value corresponding to the phase difference between the input signal and the output signal as a phase comparison output signal, and a loop filter that inputs an output signal of the phase comparison result of the digital phase comparator 1 2 and the output signal of the loop filter 2 are input to control the phase of the output signal, and this output signal is directly input to the digital phase comparator 1 or a frequency dividing circuit (not shown ) or a multiplier circuit (not shown). The first direct digital synthesizer 3 that is input via the signal, the phase synchronization unit 5 that generates the clock that is input to the digital phase comparator 1, and the offset signal is added to the output signal of the loop filter 2 by the adder 6. And a second direct digital synthesizer 4 for inputting an output signal to the phase synchronizer 5.

  The digital phase comparator 1 can be applied with a known configuration. For example, the digital phase comparator 1 counts up the clock from the phase synchronization unit 5 between the rising timings of the input signal and the output signal, and the count value is a standard value. A phase difference detection signal indicating whether the output signal of the first direct digital synthesizer 3 is a leading phase or a lagging phase can be configured depending on whether the value is larger or smaller than the value. The loop filter 2 can be configured, for example, to accumulate the phase difference detection signal for a predetermined period and output the result as a phase difference signal. Therefore, if the input signal and the output signal are in phase synchronization and the phase difference is zero, the phase difference signal is zero.

  The first direct digital synthesizer 3 for inputting the phase difference signal from the loop filter 2 has a configuration for controlling the phase of the output signal in accordance with the phase difference signal, and is already known together with the second direct digital synthesizer 4. Configuration can be applied. The second direct digital synthesizer 4 is configured such that the phase of the output signal is controlled by a signal obtained by adding an offset value by the adder 6 to the phase difference signal from the loop filter 2. Therefore, the frequency of the output signal of the second direct digital synthesizer 4 has a frequency difference corresponding to the offset value with respect to the frequency of the output signal of the first direct digital synthesizer 3.

  The output signal of the second direct digital synthesizer 4 is multiplied by the phase synchronization unit 5 to generate a clock to be input to the digital phase comparator 1. Therefore, the clock from the phase synchronization unit 5 that is phase-synchronized with the output signal of the second direct digital synthesizer 4 has a frequency ratio including a minute deviation with respect to the frequency of the output signal of the first direct digital synthesizer 3. It can be used effectively as a dither clock. Therefore, the phase difference detection accuracy can be improved.

  The offset value input to the adder 6 can be set in correspondence with the output frequency of the first and second direct digital synthesizers 3 and 4 and the frequency of the clock from the phase synchronizer 5, and is continuously fixed. However, it is also possible to periodically switch to a preset value.

  For example, assuming that the output frequency of the first direct digital synthesizer 3 is 5 MHz and the offset value is a digital value required to increase the output frequency of the direct digital synthesizer by a value corresponding to 18 Hz, the output of the second direct digital synthesizer 4 The frequency is 5,000,018 Hz. The phase synchronization unit 5 multiplies the output signal of the second direct digital synthesizer 4 by, for example, 14 to obtain an output frequency of 70,000,252 Hz, which is used as a clock signal in the digital phase comparator 1. Therefore, a clock for phase comparison including a fraction can be obtained. Note that the offset value can be set to a smaller value or a negative value. In the case of a negative value, the output frequency of the second direct digital synthesizer 4 is lower than the output frequency of the first direct digital synthesizer 3.

As described above, the phase synchronization unit 5 can be configured to output a clock having a minute frequency deviation by multiplication processing of an integral multiple that is phase-synchronized with the output signal of the second direct digital synthesizer 4 . Since the processing of the phase synchronizer 5 can be speeded up, the loop including the phase synchronizer 5 can operate at high speed, and even when an oscillator having poor noise characteristics is used for miniaturization, noise is generated by the high speed loop. The component can be suppressed. The clock input to the digital phase comparator 1 is not directly phase-synchronized with the output signal, but is phase-synchronized with the output signal of the second direct digital synthesizer 4 and has a fraction according to the offset value. Thus, the phase detection accuracy can be improved.

  FIG. 2 is an explanatory diagram of a second embodiment of the present invention, in which 21 is a digital phase comparator (DPD), 22 is a digital processing loop filter (LPF), 23 is a first direct digital synthesizer (DDS1), 24 Denotes a second direct digital synthesizer (DDS2), 25 denotes a phase synchronization unit (PLL), 26 denotes an adder, 27 denotes a multiplier, and the same name portion as in FIG. 1 has the same function.

  Similarly to the first direct digital synthesizer 3 shown in FIG. 1, the first direct digital synthesizer 23 receives the phase of the output signal according to the signal indicating the phase difference from the digital phase comparator 21 via the loop filter 22. It is controlled to synchronize with the phase of the signal. Similarly to the second direct digital synthesizer 4 shown in FIG. 1, the second direct digital synthesizer 24 also adds the offset value to the signal indicating the phase difference by the adder 26 and inputs the first direct digital synthesizer 24. With respect to the output frequency of the digital synthesizer 23, the output frequency is a difference corresponding to the offset value. The offset value is not fixed, but a signal indicating a phase difference via the loop filter 22 is multiplied by a coefficient k by a multiplier 27 to obtain an offset value.

  Therefore, the signal input from the second direct digital synthesizer 24 to the phase synchronization unit 25 follows the frequency of the output signal from the first direct digital synthesizer 23 and has a frequency difference corresponding to the offset value. It will be a thing. The output signal of the second direct digital synthesizer 24 is input to the phase synchronization unit 25, and a clock input to the digital phase comparator 21 is generated by multiplication. Also in this case, even if the multiplication in the phase synchronization unit 25 is an integer multiple, a clock having a slight frequency deviation can be generated, so that the phase synchronization unit 25 can be realized with a relatively simple configuration. it can.

  Thereby, since the phase synchronization unit 25 can process at high speed, the noise component can be suppressed by the high speed operation of the loop including the phase synchronization unit 25, and the frequency of the output signal of the second direct digital synthesizer 24 can be reduced. Since it is possible to change following the change in the frequency of the input signal at high speed, it is possible to suppress beat components generated according to the jitter frequency of the input signal. Also in the second embodiment, when the frequency of the input signal is different from that of the output signal, the output signal is divided or multiplied so that the frequency input to the digital phase comparator 21 is the same. be able to.

  FIG. 3 is an explanatory diagram of Embodiment 3 of the present invention, 31 is a digital phase comparator (DPD), 32 is a loop filter (LPF) by digital processing, 33 is a first direct digital synthesizer (DDS1), 34 Denotes a second direct digital synthesizer (DDS2), 35 denotes a phase synchronization unit (PLL), 36 denotes an adder, 37 denotes an offset value setting unit, 38 denotes a control circuit, and 39 denotes a prefilter.

  The third embodiment corresponds to a configuration in which the offset value setting unit 37, the control circuit 38, and the prefilter 39 are provided in the configuration shown in FIG. 1, and the control circuit 38 sets the offset to be set in the offset setting unit 37. The value is changed at a predetermined timing or at random timing over a long period of time, and the change width is controlled to be constant or different within a predetermined range each time. Therefore, the long-term stability as well as the short-term stability of phase synchronization can be maintained.

  Further, the order of the pre-filter 39 is changed corresponding to the change of the offset value. Accordingly, if the offset value is set to a large value, the order of the prefilter 39 is also set to a large value, and the averaging process period in the prefilter 39 is lengthened, so that the frequency of the output signal of the second direct digital synthesizer 34 is increased. Even if there is a large difference with respect to the frequency of the output signal of the first direct digital synthesizer 33, the rate of change can be slowed to maintain stability.

  FIG. 4 is an explanatory diagram of Embodiment 4 of the present invention, 41 is a digital phase comparator (DPD), 42 is a loop filter (LPF) by digital processing, 43 is a first direct digital synthesizer (DDS1), 44 Denotes a second direct digital synthesizer (DDS2), 45 denotes a phase synchronization unit (PLL), 46 denotes an adder, 47 denotes a multiplier, 48 denotes a control circuit, and 49 denotes a prefilter.

  The fourth embodiment corresponds to a configuration in which a control circuit 48 and a pre-filter 49 are provided in the configuration shown in FIG. 2, and the control circuit 48 sets a coefficient input to the multiplier 47 for each predetermined period or for a long time. The change is made at random timing over a period, and the change width is controlled to be constant or different within a predetermined range each time. Therefore, the long-term stability as well as the short-term stability of phase synchronization can be maintained.

  Further, the order of the pre-filter 49 is changed corresponding to the change of the coefficient input to the multiplier 47. Therefore, when the coefficient is increased and the offset value input to the adder 46 is set to a large value, the order of the prefilter 49 is also set to a large value, and the averaging process period in the prefilter 49 is lengthened. Even if the frequency of the output signal of the second direct digital synthesizer 44 is significantly different from the frequency of the output signal of the first direct digital synthesizer 43, the rate of change can be slowed to maintain stability. .

It is explanatory drawing of Example 1 of this invention. It is explanatory drawing of Example 2 of this invention. It is explanatory drawing of Example 3 of this invention. It is explanatory drawing of Example 4 of this invention. It is explanatory drawing of the conventional APLL. It is explanatory drawing of the conventional DPLL. It is explanatory drawing of the conventional DPLL.

Explanation of symbols

1, 21, 31, 41 Digital phase comparator (DPD)
2, 22, 32, 42 Loop filter (LPF)
3, 23, 33, 43 First direct digital synthesizer (DDS1)
4, 24, 34, 44 Second direct digital synthesizer (DDS2)
5, 25, 35 Phase synchronization part (PLL)
6, 26, 36, 46 Adder 27, 47 Multiplier 37 Offset setting unit 38, 48 Control circuit 39, 49 Pre-filter

Claims (2)

A digital phase comparator that outputs a count value of a clock corresponding to a phase difference between an input signal and an output signal as a phase comparison output signal, a loop filter that inputs a phase comparison output signal of the digital phase comparator, and the loop filter of the output signal input to the controlling the phase of the output signal, a first direct digital synthesizer for inputting an output signal through a circuit which directly or divider circuit or multiplying the digital phase comparator, the digital phase A synthesizer including a phase synchronization unit that generates the clock to be input to a comparator;
A second direct digital synthesizer that adds and inputs an offset value to the output signal of the loop filter, and inputs the output signal to the phase synchronization unit ;
The synthesizer characterized in that the frequency of the output signal of the second direct digital synthesizer has a frequency difference corresponding to the offset value with respect to the frequency of the output signal of the first direct digital synthesizer. A digital phase comparator that outputs a count value of a clock corresponding to a phase difference between an input signal and an output signal as a phase comparison output signal, a loop filter that inputs a phase comparison output signal of the digital phase comparator, and the loop filter of the output signal input to the controlling the phase of the output signal, a first direct digital synthesizer for inputting an output signal through a circuit which directly or divider circuit or multiplying the digital phase comparator, the digital phase In a synthesizer including a phase synchronization unit that multiplies a signal input to a comparator to generate the clock,
A multiplier that multiplies the output signal of the loop filter by a coefficient and outputs an offset value;
A second direct digital synthesizer that adds and inputs the offset value of the output of the multiplier and the output signal of the loop filter, and inputs the output signal to the phase synchronization unit ;
The synthesizer characterized in that the frequency of the output signal of the second direct digital synthesizer has a frequency difference corresponding to the offset value with respect to the frequency of the output signal of the first direct digital synthesizer.

Images